Test circuit and method for controlling test circuit

Cross-reference to related application

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-244322, filed on Dec. 2, 2014, the entire contents of which are incorporated herein by reference.

Field

The embodiments discussed herein are related to a test circuit and a method for controlling a test circuit.

Background

In a system in package (SiP), a plurality of semiconductor chips are embedded in a single package.

Related technology is disclosed in Japanese Laid-open Patent Publication No. 2004-317352, Japanese Laid-open Patent Publication No. 2011-81887, Japanese Laid-open Patent Publication No. 2013-105996, Japanese Laid-open Patent Publication No. 2003-309183, Japanese Laid-open Patent Publication No. 2002-185309, or Japanese Laid-open Patent Publication No. 62-169355.

Summary

According to an aspect of the embodiments, test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device from outside the semiconductor device; signal paths provided between at least one semiconductor chip included in the semiconductor chips and another semiconductor chip included in the semiconductor chips, data which is supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the at least one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating an expected value via one or more signal paths included in the signal paths, a select signal indicating the one or more signal paths which transmit the data indicating the expected value; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device from among the signal paths.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.

Brief description of drawings

FIG. 1 illustrates an example of a test circuit;

FIG. 2 illustrates another example of a test circuit;

FIG. 3 illustrates an example of a select signal generating unit and a path selecting unit;

FIG. 4 illustrates an example of a first switching unit;

FIG. 5 illustrates an example of a second switching unit;

FIG. 6 illustrates an example of a majority determination selecting unit;

FIG. 7 illustrates an example of a control method of a test circuit;

FIG. 8 illustrates another example of a test circuit;

FIG. 9 illustrates an example of a first switching unit;

FIG. 10 illustrates another example of a test circuit; and

FIG. 11 illustrates an example of a select signal generating unit.

Description of embodiments

Input/output terminals of a plurality of semiconductor chips are coupled to each other by bumps such as micro-bumps. In a semiconductor device in which a plurality of semiconductor chips are stacked, a failure may be caused in a signal path including an I/O terminal, a micro-bump or the like by manufacturing defects or the like of the micro-bump. For example, a failure in which a signal path including an I/O terminal, a micro-bump or the like is open, a failure in which wires adjacent to each other are short-circuited, or the like is caused. Accordingly, after two semiconductor chips are coupled to each other via a bump, a coupling between the semiconductor chips is tested.

A decrease of a yield (non-defective rate of a semiconductor chip) due to a bonding failure of micro-bumps increases the cost of an SiP. Therefore, for example, in a semiconductor device in which a plurality of semiconductor chips are stacked, a failure is avoided by bypassing a failure portion.

In order to detect a failure portion of a signal path between semiconductor chips, for example, a scan flip flop (a flip flop circuit designed for a scan test) which is provided in correspondence with each terminal of a test target is used. For example, in a test circuit formed in a semiconductor device, test data is set to a scan flip flop of one of the semiconductor chips coupled to each other via a scan chain or the like.

A test circuit transmits test data from a scan flip flop of one of semiconductor chips coupled to each other to a scan flip flop of the other of the semiconductor chips. The test data is retained in the scan flip flop of the other semiconductor chip. The test circuit acquires the test data retained in the scan flip flop of the other of the semiconductor chip via the scan chain or the like, and detects a failure portion of a signal path between semiconductor chips based on the acquired data.

A data retaining circuit in which an affection of malfunction of a flip flop circuit is reduced is provided by redundancy of the flip-flop circuit. For example, the data retaining circuit retains input data in three flip flops circuits, and outputs data according to a logic value which corresponds to a majority of output data of three flip flop circuits. In a semiconductor integrated circuit which is fabricated by using silicon on insulator (SOI) technology, a test circuit having a redundant configuration is provided.

A failure may be caused on a signal path for testing which is used when data is set in a scan flip flop circuit, a signal path for testing which is used when the data retained in the scan flip flop is acquired, or the like, among signal paths between chips coupled to each other. In this case, it may be difficult to perform a test for detecting a failure portion of a signal path between semiconductor chips. For example, if a failure occurs in a signal path for test, among signal paths between chips coupled to each other, the failure may not be avoided by bypassing a failure portion. Thus, yield of a semiconductor device may decrease, and a manufacturing cost of the semiconductor device may increase.

Arrows of dashed lines illustrated in the figures indicate a signal flow of data or the like.

FIG. 1 illustrates an example of a test circuit. A test circuit 10 tests a semiconductor device SEM 1 that includes a plurality of semiconductor chips 100 and 200 . The semiconductor device SEM 1 may be a system in package (SiP) in which the plurality of semiconductor chips 100 and 200 are embedded in a single package. Input/output (I/O) terminals of the plurality of semiconductor chips 100 and 200 are coupled to each other by a bump such as a micro-bump.

The test circuit 10 includes terminals TI 1 , TI 10 , TI 11 , TI 20 , TI 21 , TO 1 , TO 10 , and TO 20 , a select signal generating unit 20 , a path selecting unit 30 , and a test unit 40 .

The test input terminal TI 1 is a test input terminal to which data for testing the semiconductor device SEM 1 is input from the outside of the semiconductor device SEM 1 . The test output terminal TO 1 is an output terminal from which data corresponding to test results of the respective semiconductor chips 100 and 200 is output to the outside of the semiconductor device SEM 1 . The test input terminal TI 1 and the test output terminal TO 1 correspond to external terminals of the semiconductor device SEM 1 . For example, the test input terminal TI 1 and the test output terminal TO 1 are disposed on a surface of the semiconductor chip 100 , for example, a surface on which a logic circuit that performs a function of the semiconductor chip 100 is formed. The terminals TI 10 , TI 11 and TO 10 are disposed on a back surface of the semiconductor chip 100 . Data that is supplied to the test input terminal TI 1 is transmitted to the terminals TI 10 and TI 11 via a through-electrode or the like that passes through a substrate of the semiconductor chip 100 . Data that is input to the terminal TO 10 is transmitted to the test output terminal TO 1 via the through-electrode or the like that passes through the substrate of the semiconductor chip 100 . The terminals TI 20 , TI 21 , and TO 20 are disposed on a surface of the semiconductor chip 200 , and are respectively coupled to the terminals TI 10 , TI 11 and TO 10 via the bumps or the like.

For example, a signal path PT 1 between the terminals TI 10 and TI 20 and a signal path PT 2 between the terminals TI 11 and TI 21 are signal paths for test through which the data supplied to the test input terminal TI 1 is transmitted. A signal path PT 3 between the terminals TO 10 and TO 20 is a signal path for test through which the data supplied to the test output terminal TO 1 is transmitted. Hereinafter, the signal paths for test PT 1 , PT 2 , and PT 3 may be referred to as test paths. The test circuit 10 includes a plurality of test paths PT 1 and PT 2 through which the data supplied to the test input terminal TI 1 is redundantly transmitted.

The select signal generating unit 20 is provided in the semiconductor chip 200 that is at least one of the plurality of semiconductor chips 100 and 200 , and is coupled to another semiconductor chip 100 via the plurality of signal paths PT 1 and PT 2 . For example, the select signal generating unit 20 receives data D 10 with a logic value equal to a certain expected value from the test input terminal TI 1 via another semiconductor chip 100 and the plurality of signal paths PT 1 and PT 2 , and outputs select signals SELCTL to the path selecting unit 30 .

For example, a test device that tests the semiconductor device SEM 1 supplies the data D 10 with a logic value equal to the expected value to the test input terminal TI 1 . The data D 10 with a logic value equal to the expected value is transmitted to the select signal generating unit 20 from the test input terminals TI 1 via the plurality of signal paths PT 1 and PT 2 . The select signal generating unit 20 compares each of the data D 10 which is received via the plurality of signal paths PT 1 and PT 2 with the expected value, and generates the select signal SELCTL, based on the comparison results.

For example, if a failure, for example, an open circuit, a short circuit, or the like of the micro-bump is caused in the signal path PT 2 , among the plurality of signal paths PT 1 and PT 2 , the data D 10 transmitted to the select signal generating unit 20 via the signal path PT 2 does not coincide with the expected value. The data D 10 transmitted to the select signal generating unit 20 via the signal path PT 1 coincides with the expected value. In this case, the select signal generating unit 20 generates the select signals SELCTL indicating the signal path PT 1 . Upon receiving the data D 10 indicating the expected value via one of the plurality of signal paths PT 1 and PT 2 , the select signal generating unit 20 generates the select signals SELCTL indicating the signal paths PT through which the data D 10 indicating the expected value is transmitted.

The path selecting unit 30 is disposed in the semiconductor chip 200 including the select signal generating unit 20 , and is coupled to the plurality of signal paths PT 1 and PT 2 . The path selecting unit 30 selects the signal paths PT which are used when the semiconductor device SEM 1 is tested, among the plurality of signal paths PT 1 and PT 2 , based on the select signal SELCTL. For example, if a failure occurs in the signal path PT 2 , among the plurality of signal paths PT 1 and PT 2 , the path selecting unit 30 receives the select signal SELCTL indicating the signal path PT 1 from the select signal generating unit 20 .

In this case, the path selecting unit 30 selects the signal path PT 1 indicating the select signal SELCTL, among the plurality of signal paths PT 1 and PT 2 , as the signal paths PT between the test unit 40 of the semiconductor chip 200 and another semiconductor chip 100 . The path selecting unit 30 transmits the data received from the test input terminals TI 1 via the signal path PT 1 to the test unit 40 of the semiconductor chip 200 .

The test unit 40 is provided in each of the plurality of semiconductor chips 100 and 200 , and tests the semiconductor device SEM 1 . For example, the test unit 40 of the semiconductor chip 200 tests the semiconductor chip 200 , using the data transmitted from the path selecting unit 30 . The test unit 40 of the semiconductor chip 200 transmits the data according to the test results to the test output terminal TO 1 via the terminals TO 20 and TO 10 . For example, the test unit 40 of the semiconductor chip 100 tests the semiconductor chip 100 , using the data supplied to the test input terminal TI 1 . The test unit 40 of the semiconductor chip 100 transmits the data according to the test results to the test output terminal TO 1 .

In the test circuit 10 , if one of the test paths PT 1 and PT 2 through which the data supplied to the test input terminal TI 1 is transmitted fails, a test for detecting a failure portion of a signal path between the semiconductor chips 100 and 200 is performed. Therefore, the failure may be avoided by bypassing the failure portion. A decrease of yield due to a bonding failure between the semiconductor chips 100 and 200 may be suppressed, and a manufacturing cost of the semiconductor device SEM 1 may be reduced.

For example, a test device that tests the semiconductor device SEM 1 supplies the data D 10 with a logic value equal to the expected value to the test input terminal TI 1 . After the path selecting unit 30 selects the signal paths PT that are used at the time of testing the semiconductor device SEM 1 , the test device supplies the data that tests the semiconductor device SEM 1 to the test input terminal TI 1 . The test circuit 10 performs a test for detecting a failure portion of a signal path between the semiconductor chips 100 and 200 , using the data supplied to the test input terminal TI 1 .

For example, in a configuration of the test circuit 10 , the test paths PT (PT 1 , PT 2 ) through which the data supplied to the test input terminal TI 1 is transmitted may be configured by three or more redundant signal paths. For example, the test path PT 3 may be redundant. In this case, the select signal generating unit 20 and the path selecting unit 30 which receive data through the redundant test path PT 3 , for example, the two test paths are provided in the semiconductor chip 100 . For example, the test circuit 10 may be embedded in the semiconductor device SEM 1 in which three semiconductor chips are stacked. In this case, the select signal generating unit 20 and the path selecting unit 30 may be provided in at least two of the three semiconductor chips. The test circuit 10 may be embedded in the semiconductor device SEM 1 in which four or more semiconductor chips are stacked.

In FIG. 1 , the test circuit 10 includes the path selecting unit 30 that receives the data supplied to the test input terminal TI 1 via the plurality of signal paths PT 1 and PT 2 . The path selecting unit 30 selects the signal paths PT that are used at the time of testing the semiconductor device SEM 1 , among the plurality of signal paths PT 1 and PT 2 , based on the select signals SELCTL received from the select signal generating unit 20 . Upon receiving the data D 10 indicating the expected value via one of the plurality of signal paths PT 1 and PT 2 , the select signal generating unit 20 generates the select signals SELCTL indicating the signal paths PT through which the data D 10 indicating the expected value is transmitted.

If one of the signal paths PT 1 and PT 2 through which the data supplied to the test input terminal TI 1 is transmitted fails, a test for detecting a failure portion of the signal path between the plurality of semiconductor chips 100 and 200 is performed. Therefore, the failure may be avoided by bypassing the failure portion. Yield of the semiconductor device SEM 1 may increase.

For example, when the semiconductor device SEM 1 is tested, if the test circuit 10 which verifies operations of the semiconductor chips CHIP does not perform a normal operation, it may be determined that a logic circuit does not operate, even if the logic circuit which realizes the functions of the semiconductor chips CHIP is normal. Since abnormality of a bonding portion which bonds the plurality of semiconductor chips CHIP is avoided, yield of the semiconductor device SEM 1 may increase.

FIG. 2 illustrates another example of a test circuit. In FIG. 2 , the same or similar symbols or reference numerals will be attached to substantially the same elements as or similar elements to the elements illustrated in FIG. 1 , and detailed description thereof will be omitted or reduced. A test circuit TESC tests a semiconductor device SEM 2 which includes a plurality of semiconductor chips CHIP (CHIP 1 , CHIP 2 , CHIP 3 ). The semiconductor device SEM 2 may be an SiP in which the plurality of semiconductor chips CHIP are embedded in a single package. I/O terminals of the plurality of semiconductor chips CHIP are coupled to each other by bumps such as micro-bumps. For example, terminals which are disposed on a back surface of the semiconductor chip CHIP 1 are bonded to terminals, which are disposed on a surface of the semiconductor chip CHIP 2 , by bumps. Terminals which are disposed on a back surface of the semiconductor chip CHIP 2 are bonded to terminals, which are disposed on a surface of the semiconductor chip CHIP 3 , by bumps.

The surfaces of the respective semiconductor chips CHIP are surfaces on which logic circuits for realizing the function of the respective semiconductor chips CHIP are formed. The terminals disposed on the back surfaces of the respective semiconductor chips CHIP are coupled to the circuits or the like in the respective semiconductor chips CHIP via through-electrodes which pass through substrates of the respective semiconductor chips CHIP.

The semiconductor device SEM 2 may accept a test method standardized by a joint test action group (JTAG) as, for example, IEEE1149.1. Hereinafter, IEEE1149.1 may be referred to as the JTAG. For example, terminals for interface signals TCK (test clock), TMS (test mode select), TRST (test reset), TDI (test data in), and TDO (test data out) which are referred to as TAP (test access port), are provided in the semiconductor device SEM 2 .

The test circuit TESC includes select signal generating units SGEN, path selecting units SEL, buffers BF, first switching units SWA, second switching units SWB, a switch control unit SWCTL, majority determination selecting units MAJ, and test units TAP corresponding to the JTAG. The test circuit TESC includes the terminals TDI, TDO, TCK, TMS, and TRST which are provided in the respective semiconductor chips CHIP.

A terminal TDI 1 is a test input terminal which receives data TDI for testing the semiconductor device SEM 2 , for example, data scanned in the respective semiconductor chips CHIP from the outside of the semiconductor device SEM 2 . A terminal TDO 1 is a test output terminal which outputs data TDO corresponding to the test results of the semiconductor chips CHIP, for example, data scanned out from the respective semiconductor chips CHIP to the outside of the semiconductor device SEM 2 . Hereinafter, the data TDI and TDO is referred to as signals TDI and TDO.

A terminal TCK 1 is a test clock terminal which receives, for example, the clock signal TCK for testing (hereinafter, may be referred to as test clock TCK) from the outside of the semiconductor device SEM 2 .

A terminal TMS 1 is a test mode select terminal which receives a signal TMS for selecting a test mode (hereinafter, may be referred to as a test mode select TMS) from the outside of the semiconductor device SEM 2 . A terminal TRST 1 is a test reset terminal which receives a signal TRST for resetting a state of the test unit TAP (hereinafter, may be referred to as a test reset TRST) from the outside of the semiconductor device SEM 2 .

For example, the test input terminal TDI 1 , the test output terminal TDO 1 , the test clock terminal TCK 1 , the test mode select terminal TMS 1 , and the test reset terminal TRST 1 correspond to the external terminals of the semiconductor device SEM 2 . For example, the test input terminal TDI 1 , the test output terminal TDO 1 , the test clock terminal TCK 1 , the test mode select terminal TMS 1 , and the test reset terminal TRST 1 are disposed on a surface of the semiconductor chip CHIP 1 .

Terminals TDI 10 , TDI 11 , TDO 10 , TDO 11 , TCK 10 , TMS 10 , TMS 11 , TMS 12 , TRST 10 , TRST 11 , and TRST 12 are disposed on a back surface of the semiconductor chip CHIP 1 . Terminals TDI 20 , TDI 21 , TDO 20 , TDO 21 , TCK 20 , TMS 20 , TMS 21 , TMS 22 , TRST 20 , TRST 21 , and TRST 22 are disposed on a surface of the semiconductor chip CHIP 2 .

The terminals TDI 20 , TDI 21 , TDO 20 , and TDO 21 are respectively coupled to the terminals TDI 10 , TDI 11 , TDO 10 , and TDO 11 via bumps or the like. In addition, the terminals TCK 20 , TMS 20 , TMS 21 , TMS 22 , TRST 20 , TRST 21 , and TRST 22 are coupled to the terminals TCK 10 , TMS 10 , TMS 11 , TMS 12 , TRST 10 , TRST 11 , and TRST 12 via bumps or the like.

Terminals TDI 22 , TDI 23 , TDO 22 , TDO 23 , TCK 21 , TMS 23 , TMS 24 , TMS 25 , TRST 23 , TRST 24 , and TRST 25 are disposed on a back surface of the semiconductor chip CHIP 2 . Terminals TDI 30 , TDI 31 , TDO 30 , TDO 31 , TCK 30 , TMS 30 , TMS 31 , TMS 32 , TRST 30 , TRST 31 , and TRST 32 are disposed on a surface of the semiconductor chip CHIP 3 .

The terminals TDI 30 , TDI 31 , TDO 30 , and TDO 31 are respectively coupled to the terminals TDI 20 , TDI 21 , TDO 20 , and TDO 21 via bumps or the like. In addition, the terminals TCK 30 , TMS 30 , TMS 31 , TMS 32 , TRST 30 , TRST 31 , and TRST 32 are coupled to the terminals TCK 20 , TMS 20 , TMS 21 , TMS 22 , TRST 20 , TRST 21 , and TRST 22 via bumps or the like.

Signal paths PT 10 to PT 20 between the semiconductor chips CHIP 1 and CHIP 2 , and signal paths PT 21 to PT 31 between the semiconductor chips CHIP 2 and CHIP 3 are signal paths for testing through which signals for testing, for example, interface signals such as the data TDI are transmitted. Hereinafter, the signal paths for testing PT 10 to PT 31 may be referred to as test paths.

For example, the signal path PT 10 between the terminals TDI 10 and TDI 20 and the signal path PT 11 between the terminals TDI 11 and TDI 21 are test paths between the semiconductor chips CHIP 1 and CHIP 2 , through which the data TDI supplied to the test input terminal TDI 1 is transmitted. The signal path PT 21 between the terminals TDI 22 and TDI 30 and the signal path PT 22 between the terminals TDI 23 and TDI 31 are test paths between the semiconductor chips CHIP 2 and CHIP 3 , through which the data TDI supplied to the test input terminal TDI 1 is transmitted. The test circuit TESC includes a plurality of test paths PT 10 , PT 11 , PT 21 , and PT 22 through which the data TDI supplied to the test input terminal TDI 1 is redundantly transmitted.

The semiconductor chip CHIP 1 is a part of the test circuit TESC, and includes a switch control unit SWCTL, first switching units SWA 1 to SWA 4 , a select signal generating unit SGEN 2 , a path selecting unit SEL 2 , a second switching unit SWB, the test unit TAP, and buffers BF 1 to BF 9 .

A switch control signal (hereinafter, may be referred to as a control signal) which is output from the switch control unit SWCTL to the first switching unit SWA 1 is determined by a state of the TAP controller in the test unit TAP. In FIG. 2 , for the sake of easy viewing, signal lines between the switch control unit SWCTL and the first switching units SWA 2 to SWA 4 , the second switching unit SWB, the test unit TAP, or the like may be omitted.

The first switching units SWA (SWA 1 to SWA 4 ) are set to one of an internal transmission state and a passing-through state, based on a control signal which is received from the switch control unit SWCTL. In the internal transmission state, data which is received by the first switching units SWA, for example, the data TDI of the first switching unit SWA 1 is transmitted to the test units TAP of the semiconductor chips CHIP thereof. In the passing-through state, the data which is received by the first switching units SWA, for example, the data TDI in the first switching unit SWA 1 is transmitted to another semiconductor chip CHIP.

An input terminal of the first switching unit SWA 1 , for example, a terminal IN 10 illustrated in FIG. 4 is coupled to the test input terminal TDI 1 . One of two output terminals of the first switching unit SWA 1 , for example, one of terminals OUT 10 and OUT 11 illustrated in FIG. 4 is coupled to the terminals TDI 10 and TDI 11 via the buffers BF 1 and BF 2 , and the other of the two output terminals of the first switching unit SWA 1 is coupled to the test unit TAP.

For example, if the control signal which is received from the switch control unit SWCTL indicates the internal transmission state, the first switching unit SWA 1 transmits the data TDI transmitted from the test input terminal TDI 1 to the test unit TAP of the semiconductor chip CHIP 1 . If the control signal which is received from the switch control unit SWCTL indicates the passing-through state, the first switching unit SWA 1 transmits the data TDI transmitted from the test input terminal TDI 1 to the semiconductor chips CHIP 2 via the signal paths PT 10 and PT 11 . Accordingly, the data TDI supplied to the test input terminal TDI 1 is transmitted to a select signal generating unit SGEN 1 and a path selecting unit SEL 1 of the semiconductor chip CHIP 2 via the plurality of signal paths PT 10 and PT 11 .

An input terminal of the first switching unit SWA 2 is coupled to the test clock terminal TCK 1 . One of two output terminals of the first switching unit SWA 2 is coupled to the terminal TCK 10 via the buffer BF 3 , and the other of the two output terminals of the first switching unit SWA 2 is coupled to the test unit TAP.

An input terminal of the first switching unit SWA 3 is coupled to the test reset terminal TRST 1 . One of two output terminals of the first switching unit SWA 3 is coupled to the terminals TRST 10 , TRST 11 , and TRST 12 via the buffers BF 4 , BF 5 , and BF 6 , respectively, and the other of the two output terminals of the first switching unit SWA 3 is coupled to the test unit TAP.

An input terminal of the first switching unit SWA 4 is coupled to the test mode select terminal TMS 1 . One of two output terminals of the first switching unit SWA 4 is coupled to the terminals TMS 10 , TMS 11 , and TMS 12 via the buffers BF 7 , BF 8 , and BF 9 , respectively, and the other of the two output terminals of the first switching unit SWA 4 is coupled to the test unit TAP.

For example, if the first switching units SWA of the semiconductor chip CHIP 1 are set to the internal transmission state, the test unit TAP of the semiconductor chip CHIP 1 receives the signals TDI, TCK, TMS, and TRST from the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1 , respectively. If the first switching units SWA of the semiconductor chip CHIP 1 are set to the passing-through state, the signals TDI, TCK, TMS, and TRST supplied to the terminals TDI 1 , TCK 1 , TMS 1 , and TRST 1 , respectively, are transmitted to the semiconductor chip CHIP 2 . Even if the first switching units SWA 2 to SWA 4 are set to the passing-through state, the signals TCK, TMS, and TRST may be transmitted to the test unit TAP of the semiconductor chips CHIP thereof.

The test unit TAP performs a test corresponding to the JTAG. The test unit TAP includes a TAP controller, a command register, a data register, and the like. The TAP controller in the test unit TAP is a state machine of a synchronization type which is controlled by the signals TCK, TMS, and TRST. For example, the TAP controller generates control signals of the command register, the data register, or the like, for example, a drive clock, based on the signals TCK, TMS, and TRST.

A state of the control signal which is output from the switch control unit SWCTL is controlled by a state transition (mode) of the TAP controller. One state of the control signal may be allocated to a plurality of modes of the TAP controller.

For example, the command register in the test unit TAP is used for selecting the data register which performs a scan operation. For example, the command register receives the data TDI indicating a command code or the like, and a control signal from the TAP controller. The command code is set in the command register. For example, the data TDI indicating the command code or the like is supplied to the test input terminal TDI 1 from a test device which tests the semiconductor device SEM 2 .

The data register in the test unit TAP is a boundary scan register, a bypass register, or the like. For example, the data register receives a control signal from the TAP controller, and the data TDI supplied to the test input terminal TDI 1 , and retains the received data TDI. The data register transmits the retained data TDI to the test output terminal TDO 1 as the data TDO. The test unit TAP transmits the data TDO corresponding to the test results of the semiconductor device SEM 2 to the test output terminal TDO 1 .

Two input terminals of the select signal generating unit SGEN 2 are coupled to the terminals TDO 10 and TDO 11 . For example, the select signal generating unit SGEN 2 of the semiconductor chip CHIP 1 is coupled to the terminals TDO 20 and TDO 21 of the semiconductor chip CHIP 2 via the signal paths PT 19 and PT 20 , respectively.

For example, the select signal generating unit SGEN 2 receives the data TDO with a logic value equal to a certain expected value from the test unit TAP of another semiconductor chip CHIP 2 via the plurality of signal paths PT 19 and PT 20 , and outputs the select signals SELCTL to the path selecting unit SEL 2 .

For example, if a failure occurs in the signal path PT 20 , among the plurality of signal paths PT 19 and PT 20 , the select signal generating unit SGEN 2 receives the data TDO with a logic value equal to the expected value via the signal path PT 19 . In this case, the select signal generating unit SGEN 2 generates the select signals SELCTL indicating the signal path PT 19 , and outputs the generated select signals SELCTL to a control terminal of the path selecting unit SEL 2 .

If the select signal generating unit SGEN 2 receives the data TDO indicating the expected value via one of the plurality of signal paths PT 19 and PT 20 , the select signal generating unit SGEN 2 generates the select signals SELCTL indicating the signal paths PT that transmits the data TDO indicating the expected value.

When the test paths PT are selected, the data TDO which is transmitted from the semiconductor chip CHIP 2 to the semiconductor chip CHIP 1 is data TDI transmitted to the test unit TAP of the semiconductor chip CHIP 2 from the test input terminal TDI 1 via the semiconductor chip CHIP 1 or the like. Therefore, for example, the select signal generating unit SGEN 2 receives the data TDO with a logic value equal to the certain expected value from the test input terminal TDI 1 via another the semiconductor chip CHIP 2 and the plurality of signal paths PT 19 and PT 20 .

The two input terminals of the path selecting unit SEL 2 are coupled to the terminals TDO 10 and TDO 11 . For example, the path selecting unit SEL 2 is coupled to the terminals TDO 20 and TDO 21 of the semiconductor chip CHIP 2 via the signal paths PT 19 and PT 20 , respectively.

The path selecting unit SEL 2 selects the signal paths PT which are used at the time of testing the semiconductor device SEM 2 , among the plurality of signal paths PT 19 and PT 20 , based on the select signal SELCTL. For example, if a failure occurs in the signal path PT 20 , among the plurality of signal paths PT 19 and PT 20 , the path selecting unit SEL 2 receives the select signals SELCTL indicating the signal path PT 19 from the select signal generating unit SGEN 2 .

In this case, the path selecting unit SEL 2 selects the signal path PT 19 indicated by the select signal SELCTL, among the plurality of signal paths PT 19 and PT 20 as a signal path between the semiconductor chips CHIP 1 and CHIP 2 . For example, the path selecting unit SEL 2 transmits the data TDO received from the test unit TAP of another semiconductor chip CHIP 2 via the signal path PT 19 to the second switching unit SWB.

The second switching unit SWB is set to one of the internal transmission state and the passing-through state, based on the control signal received from the switch control unit SWCTL. In the internal transmission state, the second switching unit SWB transmits the data received from the test units TAP of the semiconductor chips CHIP thereof to the test output terminal TDO 1 . In addition, in the passing-through state, the second switching unit SWB transmits the data received from the test unit TAP of another semiconductor chip CHIP to the test output terminal TDO 1 .

For example, one of two input terminals of the second switching unit SWB, for example, one of terminals IN 20 and IN 21 illustrated in FIG. 5 is coupled to the path selecting unit SEL 2 , and the other of the two input terminals the second switching unit SWB is coupled to the test unit TAP. An output terminal of the second switching unit SWB, for example, a terminal OUT 20 illustrated in FIG. 5 is coupled to the test output terminal TDO 1 .

For example, if a control signal received from the switch control unit SWCTL indicates an internal transmission state, the second switching unit SWB transmits the data TDO transmitted from the test unit TAP to the test output terminal TDO 1 . If the control signal received from the switch control unit SWCTL indicates a passing-through state, the second switching unit SWB transmits the data TDO transmitted from the path selecting unit SEL 2 to the test output terminal TDO 1 . The data TDO transmitted via the signal paths PT selected by the path selecting unit SEL 2 , among the plurality of signal paths PT 19 and PT 20 , is transmitted to the test output terminal TDO 1 .

The semiconductor chip CHIP 2 is a part of the test circuit TESC, and includes a switch control unit SWCTL, first switching units SWA 1 to SWA 4 , a select signal generating unit SGEN 2 , a path selecting unit SEL 2 , a second switching unit SWB, a test unit TAP, and buffers BF 1 to BF 11 . The semiconductor chip CHIP 2 is a part of the test circuit TESC, and includes a select signal generating unit SGEN 1 , a path selecting unit SEL 1 , and majority determination selecting units MAJ 1 and MAJ 2 .

The select signal generating unit SGEN 1 may be substantially the same as or similar to the select signal generating unit SGEN 2 . The select signal generating unit SGEN 1 receives the data TDI with a logic value equal to the certain expected value from the test input terminal TDI 1 via another semiconductor chip CHIP 1 and the plurality of signal paths PT 10 and PT 11 , and outputs the select signals SELCTL to the path selecting unit SEL 1 .

For example, if a failure occurs in the signal path PT 10 , among the plurality of signal paths PT 10 and PT 11 , the select signal generating unit SGEN 1 receives the data TDI with a logic value equal to the expected value via the signal path PT 11 . In this case, the select signal generating unit SGEN 1 generates the select signals SELCTL indicating the signal path PT 11 , and outputs the generated select signals SELCTL to a control terminal of the path selecting unit SEL 1 . In this way, if the select signal generating unit SGEN 1 receives the data TDI indicating the expected value via one of the plurality of signal paths PT 10 and PT 11 , the select signal generating unit SGEN 1 generates the select signals SELCTL indicating the signal paths PT through which the data TDI indicating the expected value is transmitted.

The path selecting unit SEL 1 may be substantially the same as or similar to the path selecting unit SEL 2 . For example, the path selecting unit SEL 1 selects the signal paths PT which are used at the time of testing the semiconductor device SEM 2 , among the plurality of signal paths PT 10 and PT 11 , based on the select signal SELCTL.

Two input terminals of the path selecting unit SEL 1 are coupled to the terminals TDI 20 and TDI 21 . For example, the path selecting unit SEL 1 of the semiconductor chip CHIP 2 is coupled to the terminals TDI 10 and TDI 11 of the semiconductor chip CHIP 1 via the signal paths PT 10 and PT 11 , respectively. An output terminal of the path selecting unit SEL 1 is coupled to the first switching unit SWA 1 .

For example, if a failure occurs in the signal path PT 10 , among the plurality of signal paths PT 10 and PT 11 , the path selecting unit SEL 1 receives the select signals SELCTL indicating the signal path PT 11 from the select signal generating unit SGEN 1 . In this case, the path selecting unit SEL 1 selects the signal path PT 11 indicated by the select signals SELCTL among the plurality of signal paths PT 10 and PT 11 as a signal path PT between the semiconductor chips CHIP 1 and CHIP 2 . For example, the path selecting unit SEL 1 transmits the data TDI received from the test input terminal TDI 1 via the signal path PT 11 to the first switching unit SWA 1 .

The switch control unit SWCTL may be substantially the same as or similar to the switch control unit SWCTL of the semiconductor chip CHIP 1 . The first switching units SWA (SWA 1 to SWA 4 ) may be substantially the same as or similar to the first switching units SWA of the semiconductor chip CHIP 1 .

An input terminal of the first switching unit SWA 1 is coupled to an output terminal of the path selecting unit SEL 1 . One of two output terminals of the first switching unit SWA 1 is coupled to the terminals TDI 22 and TDI 23 via the buffers BF 1 and BF 2 , and the other of the two output terminals of the first switching unit SWA 1 is coupled to the test unit TAP.

For example, the first switching unit SWA 1 which is set to the internal transmission state transmits the data TDI transmitted from the path selecting unit SEL 1 to the test unit TAP of the semiconductor chip CHIP 2 . The first switching unit SWA 1 which is set to the passing-through state transmits the data TDI transmitted from the path selecting unit SEL 1 to the select signal generating unit SGEN 1 and the path selecting unit SEL 1 of the semiconductor chip CHIP 3 via the signal paths PT 21 and PT 22 , respectively.

An input terminal of the first switching unit SWA 2 is coupled to the terminal TCK 20 . One of two output terminals of the first switching unit SWA 2 is coupled to the terminal TCK 21 via the buffer BF 3 , and the other of the two output terminals of the first switching unit SWA 2 is coupled to the test unit TAP.

An input terminal of the first switching unit SWA 3 is coupled to the output terminal of the majority determination selecting unit MAJ 1 . One of two output terminals of the first switching unit SWA 3 is coupled to the terminals TRST 23 , TRST 24 , and TRST 25 via the buffers BF 4 , BF 5 , and BF 6 , respectively, and the other of the two output terminals of the first switching unit SWA 3 is coupled to the test unit TAP.

An input terminal of the first switching unit SWA 4 is coupled to the output terminal of the majority determination selecting unit MAJ 2 . One of two output terminals of the first switching unit SWA 4 is coupled to the terminals TMS 23 , TMS 24 , and TMS 25 via the buffers BF 7 , BF 8 , and BF 9 , respectively, and the other of the two output terminals of the first switching unit SWA 4 is coupled to the test unit TAP.

The description continues in the full USPTO document.