Field plate trench semiconductor device with planar gate

Technical field

This specification refers to embodiments of semiconductor devices. In particular, this specification refers to embodiments of a field plate trench semiconductor device having a planar gate. For example, such semiconductor device may exhibit one of a MOSFET structure and an IGBT structure.

Background

Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or an electric machine, rely on semiconductor devices. For example Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and diodes have been used for various applications including, but not limited to switches in power supplies and power converters.

Such power supplies or, respectively, power converters shall usually exhibit a high degree of efficiency. To this end, semiconductor devices have been proposed that exhibit a so-called compensation structure, wherein, e.g., the compensation structure can be established by means of so-called vertical field plate installed within a trench. Such compensation structure may lead to a reduction of the on-state resistance of the semiconductor device. For further reducing the amount gate charge and/or the amount of Miller charge, it has been proposed to employ a planar gate structure aligned substantially perpendicular to the vertical field plate.

Summary

According to an embodiment, a semiconductor device is presented. The semiconductor device comprises a first load contact, a second load contact and a semiconductor region configured to conduct a load current between the first load contact and the second load contact in at least a forward direction. The semiconductor region includes: a first semiconductor contact zone comprising a semiconductor body region and a semiconductor source region, the semiconductor source region being electrically connected to the first load contact and being in contact with the semiconductor body region; a second semiconductor contact zone electrically connected to the second load contact; a semiconductor drift zone coupling the first semiconductor contact zone to the second semiconductor contact zone, wherein the semiconductor body region isolates the semiconductor source region from the semiconductor drift zone. The semiconductor device further comprises, in a vertical cross-section, at least two trenches extending into the semiconductor region along an extension direction that points from the first semiconductor contact zone to the second semiconductor zone, each trench comprising a trench electrode and an insulator insulating the respective trench electrode from the semiconductor region, wherein the semiconductor region comprises a mesa zone arranged between the at least two trenches, the mesa zone including the first semiconductor contact zone. The semiconductor device is configured to establish a load current path for conduction of the load current in the forward direction, wherein the load current path comprises, in a vertical cross-section of the mesa zone, only a single inversion channel, the single inversion channel being included in the semiconductor body region.

According to a further embodiment, a further semiconductor device is presented. The further semiconductor device comprises: a first load contact, a second load contact and a semiconductor region extending along an extension direction; a surface region arranged above the semiconductor region and coupled to the semiconductor region; at least one control electrode arranged within the surface region; at least one connector trench extending into the semiconductor region along the extension direction, the at least one connector trench including a connector electrode; a contact pad arranged within the surface region; a contact runner arranged within the surface region and placed separately from both the contact pad and the at least one control electrode, the contact pad, the contact runner and the at least one control electrode being electrically coupled to each other, wherein either both the contact pad and the contact runner or both the contact runner and the at least one control electrode are electrically connected to the connector electrode of the at least one connector trench.

According to yet a further embodiment, a yet further semiconductor device is presented. The semiconductor device comprises a semiconductor region extending along an extension direction and configured to conduct a load current; a surface region arranged above the semiconductor region and coupled to the semiconductor region; at least one electrode configured to control the load current, the at least one electrode being arranged within the surface region; a connector layer, the connector layer being arranged within the surface region; a contact pad arranged within the surface region and above the connector layer; a contact runner arranged within the surface region and above the connector layer, the contact runner being placed separately from the contact pad and being electrically coupled to the at least one electrode; at least one first contact plug, the at least one first contact plug extending along the extension direction and electrically connecting the contact pad to the connector layer; at least one second contact plug, the at least one second contact plug extending along the extension direction and electrically connecting the contact runner to the connector layer.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

Brief description of the drawings

The parts in the figures are not necessarily to scale, instead emphasis being placed upon illustrating principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:

FIG. 1A schematically illustrates a section of a vertical cross-section of a semiconductor device according to one or more embodiments;

FIG. 1B schematically illustrates a section of a vertical cross-section of a semiconductor device having a multi-part trench electrode according to one or more embodiments;

FIG. 2A schematically illustrates a section of a vertical cross-section of a semiconductor device according to one or more embodiments;

FIG. 2B schematically illustrates a section of a vertical cross-section of a semiconductor device having a current-spread region according to one or more embodiments;

FIG. 2C schematically illustrates a section of a vertical cross-section of a semiconductor device having a trench with an interior region of a non-conducting material according to one or more embodiments;

FIG. 3 schematically illustrates a section of a vertical cross-section of a semiconductor device having a planar source electrode according to one or more embodiments;

FIG. 4 schematically illustrates a section of a vertical cross-section of a semiconductor device having a third semiconductor contact zone according to one or more embodiments;

FIG. 5 schematically illustrates a section of a horizontal projection of a semiconductor device according to one or more embodiments;

FIG. 6 schematically illustrates a section of a horizontal projection of a semiconductor device according to one or more embodiments; and

FIG. 7 schematically illustrates a section of a vertical cross-section of a semiconductor device according to one or more embodiments.

Detailed description

In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced.

In this regard, directional terminology, such as “top”, “bottom”, “below”, “front”, “behind”, “back”, “leading”, “trailing”, etc., may be used with reference to the orientation of the figures being described. Because parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appended claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.

The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or of a semiconductor region. This can be for instance the surface of a wafer or a die. For example, both the first lateral direction Y and the second lateral X mentioned below can be horizontal directions, wherein the first lateral direction Y and the second lateral X may be perpendicular to each other.

The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor substrate or semiconductor region. For example, the extension direction Z mentioned below may be a vertical direction that is perpendicular to both the first lateral direction Y and the second lateral X.

In this specification, n-doped is referred to as “first conductivity type” while p-doped is referred to as “second conductivity type”. Alternatively, opposite doping relations can be employed so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Further, within this specification, the term “doping concentration” may refer to an integral doping concentration or, respectively, to a mean doping concentration or to a sheet charge carrier concentration of a specific semiconductor region or semiconductor zone. Thus, e.g., a statement saying that a specific semiconductor region exhibits a certain doping concentration that is higher or lower as compared to a doping concentration of another semiconductor region may indicate that the respective mean doping concentrations of said semiconductor regions differ from each other.

In the context of the present specification, the terms “in Ohmic contact”, “in electric contact”, “in Ohmic connection”, and “electrically connected” intend to describe that there is a low Ohmic electric connection or low Ohmic current path between two regions, sections, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or a metallization or an electrode and a portion or part of a semiconductor device. Further, in the context of the present specification, the term “in contact” intends to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g., a transition between two elements being in contact with each other may not include a further intermediate element or the like.

Specific embodiments described in this specification pertain to, without being limited thereto, a power semiconductor device, e.g., to a monolithically integrated IGBT, to a monolithically integrated MOS Gated Diode (MGD) or to a monolithically integrated MOSFET that may be used within a power converter or a power supply.

The term “power semiconductor device” as used in this specification intends to describe a semiconductor device on a single chip with high voltage blocking and/or high current-carrying capabilities. In other words, such power semiconductor device is intended for high current, typically in the Ampere range, e.g., up to several ten or hundred Ampere, and/or high voltages, typically above 5 V, more typically 15 V and above.

As used within the present specification, the term “forward current” may be a current that flows in one direction through the semiconductor device, e.g., from a backside of the semiconductor device to a frontside of the semiconductor device. Such forward current may be carried, e.g., by means of a transistor cell of the semiconductor device. Further, as used within the present specification, the term “reverse current” may be a current that flows in another direction through the semiconductor device, e.g., from a frontside of the semiconductor device to a backside of the semiconductor device. For instance, such reverse current may be carried by a diode cell of the semiconductor device. In certain embodiments, the semiconductor device may be configured for carrying both a forward current and a reverse current. In other words, the semiconductor device may be operated in both a forward current mode and a reverse current mode.

FIG. 1A schematically illustrates a section of a vertical cross-section of a semiconductor device 1 according to one or more embodiments. The semiconductor device 1 comprises a first load contact 11 , a second load contact 13 and a semiconductor region 12 which can, e.g., be positioned in between the first load contact 11 and the second load contact 13 . The semiconductor device 1 may exhibit a vertical structure, meaning that the first load contact 11 , the second load contact 13 and the semiconductor region 12 can be arranged on top of each other along an extension direction Z, as illustrated in FIG. 1A .

The semiconductor region 12 can be arranged for conducting a load current between the first load contact 11 and the second load contact 13 in at least a forward direction, e.g., from the first load contact 11 to the second load contact 13 or, respectively, vice versa.

For example, the first load contact 11 may comprise a metallization layer arranged on a front side or, respectively, on a back side of the semiconductor device 1 . Correspondingly, the second load contact 13 may also comprise a metallization layer arranged on the opposite side, i.e., on the backside or, respectively, on the front side of the semiconductor device 1 . Both, the first load contact 11 and the second load contact 13 may be electrically connected to respective load terminals (not depicted in FIG. 1A ) of the semiconductor device 1 so as to allow for receiving and outputting said load current.

The semiconductor region 12 may comprise a first semiconductor contact zone 121 that may include a semiconductor source region 121 - 3 electrically connected to the first load contact 11 . For example, the semiconductor source region 121 - 3 is in contact with the first load contact 11 and may exhibit dopants of a first conductivity type. In an embodiment, the semiconductor source region 121 - 3 is a highly doped region, such as an n.sup.+-region.

In addition, the first semiconductor contact zone 121 may comprise a semiconductor body region 121 - 1 that is in contact with semiconductor source region 121 - 3 . For example, the semiconductor body region 121 - 1 may exhibit dopants of a second conductivity type complementary to the first conductivity type. In an embodiment, the semiconductor body region 121 - 1 is a doped region, such as a p-region. Thus, a transition between the semiconductor body region 121 - 1 and the semiconductor source region 121 - 3 may form a pn-junction.

The semiconductor region 12 can further comprise a second semiconductor contact zone 123 that is electrically connected to the second load contact 13 . For example, the second semiconductor contact zone 123 may also exhibit dopants of the first conductivity type and/or dopants of a second conductivity type complementary to the first conductivity type. In an embodiment, the second semiconductor contact zone 123 is a heavily doped region, such as an n.sup.++-region. Further examples of possible doping characteristics of the second semiconductor contact zone 123 will be described below.

A semiconductor drift zone 122 of the semiconductor region 12 may couple the first semiconductor contact zone 121 to the second semiconductor contact zone 123 . For example, the semiconductor drift zone 122 is a comparatively weakly doped zone, such as an n.sup.−-zone. Further, the semiconductor body region 121 - 1 may isolate said semiconductor source region 121 - 3 from the semiconductor drift zone 122 .

The semiconductor drift zone 122 may extend along said extension direction Z that may point from the first semiconductor contact zone 121 to the second semiconductor contact zone 123 . For example, the total extension of the semiconductor drift zone 122 along said extension direction Z is at least a multiple of the total extension along said extension direction Z of the first semiconductor contact zone 121 . Further, the total extension along said extension direction Z of the second semiconductor contact zone 123 may be at least a multiple of the total extension of the semiconductor drift zone 122 along said extension direction Z.

As illustrated in FIG. 1A , the semiconductor device further comprises, in the illustrated vertical cross-section, at least two trenches 14 a and 14 b that extend into the semiconductor region 12 along said extension direction Z. Each trench 14 a and 14 b may comprise a trench electrode 141 a , 141 b and an insulator 142 a , 142 b . Said insulators 142 a and 142 b may insulate the respective trench electrode 141 a , 141 b from the semiconductor region 12 . Further, said trench electrodes 141 a and 141 b may be electrically insulated from the second load contact 13 and may be electrically connected to the first load contact 11 . For example, said trench electrodes 141 a and 141 b may allow for a charge compensation within the semiconductor drift zone 122 .

In accordance with an embodiment, a path electrically connecting the trench electrodes 141 a and 141 b to the first load contact 11 may comprise a resistance region exhibiting a locally increased Ohmic resistance. Such locally increased Ohmic resistance can be achieved, e.g., by means of a reduced cross-section area of said path.

In between said two trenches 14 a and 14 b , there can be arranged a mesa zone 124 , wherein said mesa zone 124 may form a part of the semiconductor region 12 . In other words, the section of the semiconductor region 12 that is laterally confined by said two trenches 14 a and 14 b can be defined as said mesa zone 124 . The mesa zone 124 may include said first semiconductor contact zone 121 . That is to say, the first semiconductor contact zone 121 may also be arranged in between said two trenches 14 a and 14 b , e.g., in an upper region of said mesa zone 124 .

The semiconductor device 1 can be configured to establish a load current path within the semiconductor region 12 for conduction of said load current in the forward direction. Said established load current path may comprise, in the illustrated vertical cross-section of the mesa zone 124 , only a single inversion channel. Said single inversion channel is included in the semiconductor body region 121 - 1 .

For example, the established load current path for conduction of the load current in the forward direction further comprises, within said vertical cross-section of the mesa zone 124 , only one first-load-contact-to-semiconductor transition 11 - 1 within said mesa zone 124 . Said single first-load-contact-to-semiconductor transition 11 - 1 can be formed by a transition between the semiconductor source region 121 - 3 and the first load contact 11 . Further, said first-load-contact-to-semiconductor transition 11 - 1 may exhibit an area that is arranged in parallel to said extension direction Z so that the load current, when crossing said first-load-contact-to-semiconductor transition 11 - 1 flows in a direction perpendicular to said extension direction Z, e.g., in a horizontal direction. For example, the load current in the forward direction enters or, respectively leaves the mesa zone 124 by crossing said single first-load-contact-to-semiconductor transition 11 - 1 that is arranged above the trench 14 a , but, e.g., not above the trench 14 b . Thus, the load current may enter or, respectively leave the mesa zone 124 only at one sidewall of one of the trenches 14 a , 14 b that define the mesa zone 124 , e.g., only in vicinity to the trench electrode 141 a , and not in vicinity to the trench electrode 141 b , i.e., not at one or more central points of the upper boundary of the mesa zone 124 defined by said insulation region 151 along a first lateral direction Y. For example, the insulator 142 b of the trench 14 b may be arranged so as to insulate the first load contact 11 from the mesa zone 124 , as illustrated in FIG. 1A , wherein other configurations of the insulator 142 b are also possible, which will be explained in more detail with regards to FIGS. 3 and 4 . In contrast, the insulator 142 a of the trench 14 a may be arranged such that said first-load-contact-to-semiconductor transition 11 - 1 may be established between the semiconductor source region 121 - 3 and the first load contact 11 .

Further, the established load current path for conduction of the load current in the forward direction may further comprise said pn-junction that can be formed by a transition between the semiconductor body region 121 - 1 and the semiconductor source region 121 - 3 , as explained above.

It shall be noted that the term “inversion channel”, as used within the specification, intends to describe a type of charge carrier being present within the semiconductor body region 121 - 1 . For example, if the semiconductor body region 121 - 1 exhibits dopants of the second conductivity type, e.g., acceptors, said single inversion channel included in the established load current path may be substantially formed by electrons. In another embodiment, if the semiconductor body region 121 - 1 exhibits dopants of a first conductivity type, e.g., donors, said single inversion channel may be substantially formed by holes.

As illustrated in FIG. 1A , the semiconductor device 1 may further comprise a control electrode 15 arranged above said first semiconductor contact zone 121 , i.e., above the mesa zone 124 . The control electrode 15 can be electrically insulated from both the first load contact 11 and the second load contact 13 . To this end, the control electrode 15 may be surrounded by an insulation region 151 , wherein the insulation region 151 may be in contact with the first semiconductor contact zone 121 and be arranged above said mesa zone 124 . Further, the control electrode 15 can be electrically insulated from the trench electrodes 141 a and 141 b.

Further, the control electrode 15 may exhibit a planar structure that is aligned to the first semiconductor contact zone 121 with respect to said extension direction Z so as to cover at least a part of the first semiconductor contact zone 121 , e.g., at least a part of the semiconductor source region 121 - 3 and a part of the semiconductor body region 121 - 1 . For example, each of the semiconductor source region 121 - 3 , the semiconductor body region 121 - 1 and the control electrode 15 exhibit an overlap in the first lateral direction Y.

It shall be noted that the term “planar structure”, as used herein, may refer to a structure that is arranged above said first semiconductor contact zone 121 and, e.g., not arranged laterally, i.e., in said first lateral direction Y, adjacent to said first semiconductor contact zone 121 . In an embodiment, the control electrode 15 is arranged above said first semiconductor contact zone 121 such that it covers at least a part of said first semiconductor contact zone 121 , e.g., at least a part of the semiconductor body region 121 - 1 , at least a part of the semiconductor source region 121 - 3 and a section of said semiconductor drift zone 122 that is included in the mesa zone 124 . Thus, there may be an overlap along said first lateral direction Y of the lateral extension of the control electrode 15 on the one side and of the lateral extensions of the semiconductor source region 121 - 3 , the semiconductor body region 121 - 1 and of the semiconductor drift region 122 on the other side. Further, “planar structure” may refer to a structure that is entirely arranged above the semiconductor region 12 .

For example, the control electrode 15 may be electrically connected to a gate terminal (not illustrated in FIG. 1A ) of the semiconductor device 1 . Further, the first load contact 11 may form a part of or be electrically connected to a source terminal (not illustrated in FIG. 1A ) of the semiconductor device 1 , and the second load contact 13 may form a part of or be electrically connected to a drain terminal (not illustrated in FIG. 1A ) of the semiconductor device 1 . For example, the semiconductor device 1 is arranged and configured for establishing said load current path for conduction of said load current in the forward direction in dependence of a difference between an electrical potential of the control electrode 15 and an electrical potential of said first load contact 11 . For example, said difference may be generated by applying a voltage between the first load contact 11 and the control electrode 15 . Such voltage may, e.g., be provided by a gate driver (not illustrated) coupled to the semiconductor device 1 .

As will be explained in more detail with regards to FIGS. 5 to 7 , the control electrode 15 may be, in accordance with an embodiment, electrically coupled to a contact pad of the semiconductor device 1 by means of a contact runner and by means of one of a connector electrode of a connector trench and a connector layer, wherein said contact pad may be arranged to be contacted by a bond wire or a clip for receiving a control signal, e.g., a gate signal provided by a gate driver. Further aspects of this optional feature of the semiconductor device 1 will be explained below.

For example, at least one of the trench electrodes 141 a and 141 b may be in contact with the first load contact 11 . Thus, the trench electrodes 141 a and 142 b may exhibit substantially the same electrical potential as the first load contact 11 . For example, each of said trench electrodes 141 a and 141 b comprises a field plate electrode. Said field plate electrodes may each be arranged perpendicular to the planar structure of the control electrode 15 . Further, each of said trench electrodes 141 a and 141 b may be a single monolithic electrode. Also, as schematically illustrated in FIG. 1A , each of the trench electrodes 141 a and 141 b may extend further into the semiconductor region 12 along said extension direction Z as compared to the first semiconductor contact zone 121 .

In an embodiment, a distance P, also referred to as “pitch”, between said two trenches 14 a and 14 b in said first lateral direction Y that is perpendicular to said extension direction Z amounts to less than 3 μm, e.g., to less than 2 μm, or even to less than 1 μm. In an embodiment, the pitch P may amount to less than 0.5 μm. Such low pitch may allow for a reduction of both the on-state resistance of the semiconductor device 1 as well as a reduction of the output charge of the semiconductor device 1 . For example, within said cross-section of the mesa zone 124 , there is only arranged a single first semiconductor contact zone 121 due to the low pitch P, i.e., only a single semiconductor source region 121 - 3 . That is to say, within said vertical cross-section of the mesa zone 124 , there may be arranged only one coherent semiconductor source region 121 - 3 . Thus, the semiconductor device 1 may exhibit an asymmetrical structure within said mesa zone 124 , since, as explained above, the load current in the forward direction enters or, respectively leaves the mesa zone 124 by crossing said single first-load-contact-to-semiconductor transition 11 - 1 that is arranged above the trench 14 a , but, e.g., not above the trench 14 b . Thus, the load current may enter or, respectively leave the mesa zone 124 only at one sidewall of one of the trenches 14 a , 14 b that define the mesa zone, e.g., only in vicinity to the trench electrode 141 a and not in vicinity to the trench electrode 141 b , i.e., not in the middle of the mesa zone 124 . For example, the insulator 142 b of the trench 14 b may be arranged so as to insulate the first load contact 11 from the mesa zone 124 , as illustrated in FIG. 1A . In contrast, the insulator 142 a of the trench 14 a may be arranged such that said first-load-contact-to-semiconductor transition 11 - 1 may be established between the semiconductor source region 121 - 3 and the first load contact 11 . Accordingly, the structure as schematically illustrated in FIG. 1A may then exhibit, in the vertical cross-section, only one inversion channel.

In accordance with an embodiment, the width W.sub.M of the mesa zone 124 along said first lateral direction Y amounts to less than 3.0 μm, to less than 1.5 μm, to less than 1 μm, or even to less than 0.5 μm. For example, said width W.sub.M is measured as a distance between the sidewalls of the trenches 14 a and 14 b that laterally confine said mesa zone 124 , wherein said distance may be measured at a level of the transition between said semiconductor body region 121 - 1 and said semiconductor drift zone 122 , for example at a deepest point of said transition with regards to said extension direction Z, as schematically illustrated in FIG. 1A . Said pitch P may also be determined at said deepest point.

Further, said width W.sub.M of the mesa zone 124 may be smaller as compared to the width W.sub.T along said lateral direction of each of the trenches 14 a and 14 b , wherein said width W.sub.T along said lateral direction of each of the trenches 14 a and 14 b may be measured at a level of the transition between said semiconductor body region 121 - 1 and said semiconductor drift zone 122 , for example at a deepest point of said transition with regards to said extension direction Z, as schematically illustrated in FIG. 1A .

In accordance with an embodiment, each insulator 142 a and 142 b of the trenches 14 a and 14 b may exhibit, in said first lateral direction Y, a homogenous, e.g., a constant thickness along substantially the total extension of the respective trench in the extension direction Z. This may allow for a reduction of the complexity of the manufacturing process. In another embodiment, said insulator thickness may increase along the extension direction Z at least partially.

For example, some of the components illustrated in FIG. 1A of the semiconductor device 1 may form a part of a transistor cell that is configured to carry said load current in the forward direction, such as the trenches 14 a , 14 b , the control electrode 15 and the first semiconductor contact zone 121 .

FIG. 1B schematically illustrates a section of a vertical cross-section of a semiconductor device 1 having multi-part trench electrodes 141 a and 141 b according to one or more embodiments. Besides said trench electrodes 141 a and 141 b , the semiconductor device 1 illustrated in FIG. 1B is substantially identical to the semiconductor device 1 illustrated in FIG. 1A . In so far, the description of FIG. 1A also applies to FIG. 1B . In accordance with the embodiment of FIG. 1B , the trench electrodes 141 a and 141 b comprise a respective first electrode part 141 a - 1 , 141 b - 1 as well as a respective second electrode part 141 a - 2 , 141 b - 2 . These two parts may be electrically insulated from each other by means of said insulator 142 a or, respectively, 142 b.

Said first electrode parts 141 a - 1 and 141 b - 1 may be arranged in an upper region of the respective trench 14 a , 14 b and may both be in contact with the first load contact 11 . Thus the first electrode parts 141 a - 1 and 141 b - 1 may exhibit the same electrical potential as the first load contact 11 .

The second electrode parts 141 a - 2 and 141 b - 2 may each be arranged in a bottom region of the respective trench 14 a , 14 b . These parts may either also be electrically connected to the first load contact 11 and thus exhibit the same electrical potential as the first load contact 11 or, respectively, said second electrode parts 141 a - 2 and 141 b - 2 may be electrically insulated from the first load contact 11 . In the latter case, another electrical potential can be applied to the second electrode parts 141 a - 2 and 141 b - 2 . For example, said second electrode parts 141 a - 2 and 141 b - 2 may be electrically coupled to the first load contact 11 by means of a path that exhibits a higher Ohmic resistance than an electrical connection between the first electrode parts 141 a - 1 , 141 b - 1 and the first load contact 11 . For example, the higher Ohmic resistance may allow for reducing the magnitude of voltage and/or current transients, e.g., during switching operation of the semiconductor device 1 . Said path can be established, e.g., by means of at least a connector trench, wherein exemplary embodiments of such type of a trench will be explained in more detail with respect to FIG. 5 and FIG. 6 . Thus, in accordance with an embodiment, said connector trench (not illustrated in FIG. 1B ) that may couple the second electrode parts 141 a - 2 and 141 b - 2 to the first load contact 11 can extend into the semiconductor region 12 along said extension direction Z and may include a connector electrode that may also extend along said extension direction Z. Both the second electrode parts 141 a - 2 , 141 b - 2 and the first load contact 11 may be electrically connected to said connector electrode. Further, the connector electrode can comprise a resistance region exhibiting a locally increased Ohmic resistance so as to increase a total Ohmic resistance in said path that electrically couples the first load contact 11 to the second electrode parts 141 a - 2 , 141 b - 2 . For example, the resistance region of the connector electrode is produced by a locally decreased cross-section area of the connector electrode.

Such multi-part trench electrodes 141 a and 141 b may further allow for a reduced thickness of the respective insulator 142 a , 142 b in an upper region of the respective trench 14 a , 14 b , which may lead to an increased compensation and, thus, to a reduced on-state resistance of the semiconductor device 1 .

FIG. 2A to FIG. 2C each schematically illustrate a section of a vertical cross-section of a semiconductor device 1 in accordance with one or more embodiments. However, the principle setup of each of the semiconductor devices illustrated in FIG. 2A to FIG. 2C essentially corresponds to the setup of the semiconductor device 1 illustrated in FIG. 1A . Thus, what has been stated above with regards to the embodiment as illustrated in FIG. 1A may also apply to the semiconductor device 1 illustrated in FIG. 2A to FIG. 2C , if not stated otherwise.

In accordance with the embodiments illustrated in FIG. 2A to FIG. 2C , the semiconductor device 1 may comprise a first load terminal 17 electrically connected to the first load contact 11 . For example, the first load terminal 17 is a source (S) terminal of the semiconductor device 1 . Further, the semiconductor device 1 may comprise a second load terminal 19 electrically connected to the second load contact 13 . For example, the second load terminal 19 is a drain (D) terminal of the semiconductor device 1 . Further, the semiconductor device 1 may comprise a control terminal 18 connected to the control electrodes 15 a and 15 b . For example, the control terminal 18 is a gate (G) terminal of the semiconductor device 1 . Each of the control electrodes 15 a and 15 b may exhibit a planar structure, e.g., each of the control electrodes 15 a and 15 b may be arranged entirely above said semiconductor region 12 .

In an embodiment, the semiconductor device 1 may be controlled by applying a voltage between the first load terminal 17 and the control terminal 18 . Thus, the semiconductor device 1 may be arranged and configured for establishing said load current path in dependence of the voltage applied to the first load terminal 17 and the control terminal 18 . For example, the load current can be received and output by means of said load terminals 17 and 19 .

As illustrated in FIG. 2A to FIG. 2C , the semiconductor device 1 may exhibit a plurality of mesa zones 124 a , 124 b , wherein each mesa zone 124 a , 124 b is arranged between two respective trenches, e.g., mesa zone 124 a is arranged between trenches 14 a and 14 b . Further, as explained with respect to FIG. 1A , each mesa zone 124 a , 124 b may comprise a first semiconductor contact zone 121 a , 121 b . Each first semiconductor contact zone 121 a and 121 b may comprise a semiconductor source region 121 - 3 a , 121 - 3 b . For example, within the vertical cross-section of each mesa zone 124 a and 124 b , there is only arranged one respective coherent semiconductor source region 121 - 3 a , 121 - 3 b . Thus, in accordance with an embodiment, there may only be one first-load-contact-to-semiconductor transition 11 - 1 a and 11 - 1 b within each mesa zone 124 a , 124 b . Above each mesa zone 124 a and 124 b , there may be arranged a respective control electrode 15 a and 15 b . As explained with respect to FIG. 1A , each of said control electrodes 15 a and 15 b may exhibit said planar structure. Further, each control electrode 15 a and 15 b may be insulated from the semiconductor region 12 by a respective insulation region 151 a , 151 b , 151 c . Each control electrode 15 a and 15 b may be electrically connected to said control terminal 18 of the semiconductor device 1 and may be electrically insulated from both the first load contact 11 and the second load contact 13 .

The semiconductor device 1 may include a plurality of transistor cells formed by a respective pair of trenches 14 a , 14 b , the control electrode 15 a arranged above the mesa zone 124 a that is laterally confined by said pair of trenches 14 a , 14 b , and the first semiconductor contact zone 121 a arranged within the mesa zone 124 a , wherein said plurality of transistor cells may be arranged adjacent to each other along said first lateral direction Y and may each extend along the second lateral direction X, thereby yielding, e.g., a stripe cell configuration of the semiconductor device 1 . In another embodiment, the arrangement of said cells may exhibit a grid pattern. The extension in the second lateral direction X, however, is not illustrated in FIG. 1A-4 . Thus, each of the trenches 14 a and 14 b may exhibit one of the following forms: a stripe form (wherein, e.g., the total extension along the second lateral X direction is at least a multiple of the total extension along said extension direction Z), a needle form (wherein, e.g., the total extensions along the first and second lateral directions X and Y are similar to each other and both smaller than the total extension along said extension direction Z) and a grid form (wherein, e.g., the trench electrodes exhibit plate sections arranged substantially perpendicular to each other, e.g., arranged in XZ-planes and in YZ-planes).

The description continues in the full USPTO document.