Isolated flyback converter

Background

Power converters are ubiquitous in modern electronics, appliances, devices, computers, vehicles, and are an especially important part of renewable energy. A power converter is used to convert the voltage or current from a source of electricity to a voltage or current having different characteristics. For example, the power converter may convert an incoming voltage to a lower voltage, to a higher voltage, to a different voltage reference point, may converted AC to DC, DC to AC, etc. Most modern power regulators are of the “switching” type, in which a semiconductor switch periodically applies and interrupts a flow of electricity through the converter. In many such devices, the efficiency of the converter depends on the control-algorithm for operating the switch. For simplicity, conventional power converters employ a fixed switch period. The width or duty cycle of the switch operation is controlled to establish the converter characteristic.

Conventional converters perform poorly at low power because the required switch duty cycles are excessively short. To alleviate this problem, some advanced controllers use a “pulse-skipping” algorithm in which the switch period is increased in discrete multiples. Other converters operate with substantially constant switch duration and a variable switch frequency, which have efficiency problems at high power. Some conventional power converters switch between various modes of operation depending on the magnitude of the load.

Summary

Embodiments of the present invention are generally related to power converters. Specifically, some embodiments of the present invention provide techniques for switch control and design of an isolated flyback converter which extends the efficient operating envelope and maximizes efficiency throughout the envelope. Some embodiments of the present invention provide a method to develop optimal switch algorithms for a more general class of power converters, e.g., buck, boost, buck/boost, flyback, SEPIC, Cuk, resonant, soft-switching, etc. In some embodiments, both the frequency and duration of the switch operation are optimized for the source and load characteristics to realize the highest level of efficiency supported by the hardware. In some embodiments, such switching algorithms result in reduced circuit stresses, soft switching, reduced electromagnetic emissions, in addition to improved efficiency. Embodiments of the present invention provide ways to reduce the cost of a converter to achieve target efficiency or operating envelope. In other embodiments, techniques are provided that can increase the power efficiency and operating envelope of a given converter without a substantial increase in cost.

The following detailed description, together with the accompanying drawings will provide a better understanding of the nature and advantages of the embodiments of the present invention.

Brief description of the drawings

FIG. 1A illustrates a block diagram of a flyback converter having a controller that senses input and output parameters according to an embodiment of the present invention.

FIG. 1B is a block diagram of a flyback converter having a controller that senses only input-side parameters according to an embodiment of the present invention.

FIG. 1C is a block diagram of a flyback converter having a controller that senses input-side parameters and receives output-side parameter information across a communication channel according to an embodiment of the present invention.

FIG. 1D is a block diagram of a flyback converter according to an embodiment of the present invention.

FIG. 1E is a block diagram of a flyback converter according to another embodiment of the present invention.

FIG. 2A shows a schematic diagram of an isolated flyback converter power circuit having a novel trans-winding capacitor according to an embodiment of the present invention.

FIG. 2B shows a schematic diagram of an isolated flyback converter including input and output sensing circuitry according to an embodiment of the present invention.

FIG. 3A illustrates voltage waveforms in a secondary winding of an isolated flyback converter at a sub-optimal switch setting according to an embodiment of the present invention.

FIG. 3B illustrates voltage waveforms across the switch of an isolated flyback converter at the same sub-optimal switch setting as in FIG. 3A , according to an embodiment of the present invention.

FIG. 3C shows voltage waveforms across the switch of an isolated flyback converter at a different sub-optimal switch setting according to an embodiment of the present invention.

FIG. 4 illustrates modulation of converter efficiency with input current at different switch frequencies in an isolated flyback converter according to an embodiment of the present invention.

FIG. 5 illustrates modulation of converter efficiency and input current at different switch widths at constant switch period according to an embodiment of the present invention.

FIG. 6 shows a plot of switch periods vs. input current that produce the peak efficiency for any switch setting and a plot of the best realized efficiency according to an embodiment of the present invention.

FIG. 7 shows a plot of the ring duration calculated from the switch periods in FIG. 6 , according to an embodiment of the present invention.

FIG. 8 shows an overlay of optimal switch periods vs. input current at different input and output voltages according to an embodiment of the present invention.

FIG. 8A is a flow diagram illustrating a method for calculating switch setting according to an embodiment of the present invention.

FIG. 9A shows an overlaid plot of a band-slope coefficient vs. voltage ratio parameter and a best fit to a theoretical function according to an embodiment of the present invention.

FIG. 9B shows an approximate decomposition of the theoretical function in FIG. 9A into piece-wise quadratic and linear segments.

FIG. 10A shows an overlaid plot of a band-intercept coefficient vs. voltage ratio parameter and an approximation based on piece-wise quadratic and linear segments, according to an embodiment of the present invention.

FIG. 10B shows details of the quadratic and linear segments comprising the approximation in FIG. 10A , according to an embodiment of the present invention.

FIG. 11 shows a comparison of optimum period modeled in a controller with measured results according to an embodiment of the present invention.

FIG. 12 shows a control signal comprising a finite difference derivative of current with respect to a perturbation in switch width and period and the correspondence of sharp minima with efficiency peaks, according to an embodiment of the present invention.

FIG. 13 shows the variation of switch width and period at constant input current and the corresponding variation of efficiency according to an embodiment of the present invention.

FIG. 14A shows a switch voltage waveform after convergence of a closed loop controller at an input current of 0.1 A according to an embodiment of the present invention.

FIG. 14B shows a switch voltage waveform as in FIG. 14A , at an input current of 0.2 A according to another embodiment of the present invention.

FIG. 14C shows a switch voltage waveform as in FIG. 14A , at an input current of 0.5 A according to yet another embodiment of the present invention.

FIG. 14D shows a switch voltage waveform as in FIG. 14A , at an input current of 1.0 A according to still another embodiment of the present invention.

FIG. 14E shows a switch voltage waveform as in FIG. 14A , at an input current of 1.5 A according to an embodiment of the present invention.

FIG. 14F shows a switch voltage waveform as in FIG. 14A , at an input current of 2.0 A according to an embodiment of the present invention.

FIG. 14G shows a switch voltage waveform as in FIG. 14A , at an input current of 3.0 A according to an embodiment of the present invention.

FIG. 14H shows a switch voltage waveform as in FIG. 14A , at an input current of 3.9 A, according to an embodiment of the present invention.

FIG. 15 shows an overlay of efficiency measurements vs. input current of a converter over a range of input and output voltages according to an embodiment of the present invention.

Detailed description

Isolated flyback converters may be useful in a wide range of applications because of their relative low cost, ability to step up or down via changing the winding ratio on the flyback transformer, and the ability to boost and buck from this step-up/step-down point. Embodiments of the present invention provide a method to control the flyback switch period and on-time, or width, to maximize efficiency for a given set of hardware. Some embodiments of the present invention provide self-protection calculations that may be employed to limit operation of a flyback converter to a safe working envelope. Another embodiment of the present invention provides an apparatus to implement a flyback switch control.

In some embodiments, a method to develop the switch control scheme for a given hardware configuration is provided. Advantages of applying an embodiment of the present invention may include reduction of voltage and current stresses and thermal loads, the reduction of electromagnetic emissions (EMI/RFI), the maximization of efficiency over the operating envelope, and a substantial extension of the operating envelope of input and output voltages and currents.

Flyback converters are used in a wide variety of electronic equipment. FIG. 1A shows a block diagram of a converter 100 that processes power from a source 102 to a power sink 104 . Converter 100 includes a power circuit 106 and a controller 108 . Controller 108 produces at least one switch-control signal 110 , e.g., as a train of voltage or current pulses. Some embodiments of the present invention utilize measurements of input characteristics 112 , e.g., input voltage or input current, and measurements of output characteristics 114 e.g., output voltage or output current, in open loop calculations of switch timing and closed-loop adjustments of switch timing.

FIG. 1B shows a converter 120 according to another embodiment of the present invention. Controller 120 includes an advanced controller 122 that utilizes only measurements taken on the input side to control switch timing. Controller 122 may infer output characteristics, e.g., output voltage, from their effect on characteristics of the input, e.g., histories or waveforms of voltage and current across at least one internal component, e.g., a switch, a transformer, an inductor, a resistor, or a capacitor, input voltage or current variation with switch period and or width, etc. Because analog sensing circuitry can increase the cost and complexity of a converter, an objective of this invention is to minimize this circuitry and its cost while not compromising control and efficiency. Controller 122 utilizes only output characteristics rather than input characteristics.

FIG. 1C shows a converter 140 according to yet another embodiment of the present invention. Convertor 140 includes a controller 142 and a secondary controller 144 . Secondary controller 144 may sense at least one output characteristic 146 , e.g., output voltage, and report this information using a communication channel 148 to controller 140 . As used herein, communication channel 148 may comprise an isolated or non-isolated circuit. Communication channel 148 may convey data in a digital or analog encoding. Transmission may be asynchronous, synchronous transmission, I.sup.2C, SPI, one-wire, two-wire, etc. Physical hardware for communication channel 148 may comprise a direct connection, AC-coupled circuit, differential circuit, current-loop, radio-frequency link, etc. Data encoding for communication channel 148 may be analog voltage or current, pulse-width modulation (PWM), amplitude modulation (AM), frequency modulation, phase modulation (PM), return-to-zero (RZ), non-return-to-zero (NRZ), inverted non-return-to-zero (NRZI), enhanced non-return-to-zero (ENRZ), Manchester encoding, and the like as is known by one skilled in the art. In some embodiments, secondary controller 144 may be external to converter 140 . In other embodiments, secondary controller 144 may be part of converter 140 .

FIG. 1D shows a block diagram of a flyback controller 160 according an embodiment of the present invention. In converter 160 , the control of the switching is functionally split between a switch-width controller 162 and switch-period controller 164 . Fine dashed lines in FIG. 1D depict alternative arrangements. Such a functional decomposition may be desirable to provide a rapid response to load, supply, or power variations, e.g., via a high-speed digital, analog, or hybrid closed-loop controller (e.g., switch-width controller 162 ), while higher-level control logic employed to set the switch period to optimize efficiency may be performed by switch-period controller 164 operating at a different, possibly lower, control-system bandwidth. In some embodiments, switch-period controller 164 may provide an analog, digital, PWMed, or otherwise communicated set point 166 to switch-width controller 162 to control a switch width. A set point as described herein is defined as a parameter from which an error signal is derived, the minimization of which is a function of a control loop. For example, a set point may be a target input or output voltage, current, or power, that is communicated to switch-width controller 162 via an analog signal that is related, e.g., proportionally, logarithmically, exponentially, etc., to that target. Switch-width controller 162 may comprise a circuit that produces an error signal from the sum or difference between this analog signal and a measured analog signal derived from the corresponding instantaneous input or output parameter. In some embodiments, this error signal and its time integrals and derivatives may be combined to produce a feedback signal that changes an output parameter, such as the switch width. In some embodiments, set point 166 may be encoded via one or more discrete passive or active components, such as resistors, voltage references, operations amplifiers, or circuit connections as known in the art. In some embodiments, switch-period controller 164 may produce a clocking signal 168 that is used by switch-width controller 162 to coordinate the switch period. In some embodiments, clocking signal 168 may include a pulse train at substantially a desired frequency or multiple or sub-harmonic thereof. Switch-width controller 162 produces a switching signal 110 . The resulting switch width may be measured by switch-period controller 164 via a connection 170 or an analogous or communication signal 172 in a control-loop feedback. Control loop initiation and operation of controllers 162 and 164 may require information about input parameter 112 and output parameter 114 . In some embodiments, some information used in switch-period controller 164 may be supplied via a communication channel 148 from a secondary controller 144 .

FIG. 1E shows a block diagram of a flyback converter 180 according to another embodiment of the present invention. In this embodiment, flyback converter 180 includes a switch microcontroller 182 . Switch microcontroller may be implemented as a single integrated circuit having a single or multiple processors. In some embodiments, each of the processor may be a single-core or multiple-core processor. Switch microcontroller 182 may have internal memory 185 that stores instructions for operation of switch microcontroller 182 . In other embodiments, the memory may be external to switch microcontroller 182 but included in flyback converter 180 .

Core and arithmetic and logic unit 184 of switch microcontroller 184 may execute an algorithm that results in settings of a hardware pulse-width-modulation peripheral 186 that produce a switch signal 110 . Alternatively, switch microcontroller 184 may synthesize switch signal 110 using judiciously timed firmware, e.g., via the use of high-speed interrupts, especially in concert with a hardware timer, or via carefully timed execution loops. Switch microcontroller 182 may include an analog-to-digital (A/D) converter 190 to digitize measurements for use in a control algorithm. In some embodiments, switch microcontroller 182 may also include an analog multiplexor 192 that may provide time-sharing a single-channel A/D between a plurality of signals. The plurality of signals may include input parameters 112 , output parameters 114 , and proximate ambient condition information 194 , such as temperature. Core and arithmetic and logic unit 184 may further receive information via a communications peripheral 196 connected to a communication channel 148 . In some embodiments, communications peripheral 196 may be connected to a secondary controller 144 via communication channel 148 . In some embodiments, secondary controller 144 may measure and communicate proximate or averaged ambient conditions 198 of importance in a control loop, e.g., temperature, heat flux, temperature gradients in space and time, atmospheric pressure, humidity, wind speed, insolation, and the like. In some embodiments, core and arithmetic and logic unit 184 may receive commands via communications peripheral 196 . In some embodiments, such commands may include instructions for setting control-system target parameters, setting calibration parameters, setting new firmware, setting control system algorithms, setting raw switch parameters, setting derating conditions and limits, and/or setting control-system parameters, etc.

In some embodiments, the core and arithmetic and logic unit 184 may transmit information including internal settings, registers, error counters, versions, operating history, data logs, real-time data, operating time, cumulative data, raw measurements, calibrated measurements, control-system activity, control-system state, control-system error state to a secondary controller (e.g., controller 144 ), an external control device, or an external monitoring device directly or through at least one intermediary controller. As used herein, an external control is a device that issues at least one command across a communication channel (e.g., communication channel 148 ) that changes an internal state of a controller (e.g., switch microcontroller 182 ). An external monitor is a device that receives at least one datum from a controller across a communication channel. As used herein, an intermediary controller passes data from one communication channel to another. Examples of external control and monitor devices include but are not limited to computers, browsers, application software, drivers, smart phones, cell phones, remote displays, remote controls, external controls, external displays, television sets, telephones, radios, and the like. Intermediate controllers may use a combination of wired, optical, or wireless communications including, but not limited to, blue-tooth, WiFi, Zigbee, IEEE 802-compliant protocols, CDMA, 3G, 4G, RS485, RS232, USB, SATA, PCI, PCI express, POTs, Ethernet, and other communication schemes well-known in the art.

Measurement data may include internal bandgap data, input current, input voltage, output voltage, temperature, logic-voltage, switch period, switch width, finite-difference derivatives, covariances, noise levels, rms variations, and the like. In some embodiments, switch microcontroller 184 may log or report information such as detected errors, changes in detected parameters, increases in noise levels and variations that may be symptomatic of hardware problems. In other embodiments, switch microcontroller 184 may execute one or more specialty algorithms on command, occasionally, periodically, or continuously. Examples of these algorithms include but are not limited to state-of-hardware and firmware health checks, auto-calibration procedures, firmware updates, automated testing support routines, power optimization routines, maximum power-point tracking, solar-panel power balancing routines, battery-charge balancing routines, battery discharge balancing routines, and the like.

FIG. 2A shows a schematic diagram 200 of an isolated flyback controller power circuit, e.g., power circuit 106 of FIG. 1A , according to an embodiment of the present invention. A switch 202 , e.g., a semiconductor switch such as a transistor, MOSFET, IGBT, and the like, may periodically supply electrical energy via an “input voltage” and “input current” to one side 204 of a transformer 206 , herein called the “primary” or “input” side, which stores a significant part of this energy magnetically. When switch 202 is opened, a significant part of this stored magnetic energy transfers to one or more isolated or coupled windings 208 , herein called a “secondary” or “output” side, typically providing current through a rectifier 210 , e.g., diode or synchronous rectifier, to a filter circuit 212 to smooth the resulting voltage, herein called the “output voltage.” One of the advantages of the isolated flyback converter is that the output can be electrically isolated from the input; however, some applications may not need this isolation and may couple one or more of the outputs to the inputs either directly or via intermediary active or passive circuitry. As used herein, the term “isolated flyback” comprises these non-isolated or incompletely isolated circuits where the method of operation of the converter circuit is substantially similar to that of an isolated flyback converter.

During the dynamics of this power transfer, energy stored in the leakage inductance of the transformer is also released and may typically appear as a spiking voltage across switch 202 and may be many multiples of the input voltage if there is no voltage limiting, such as avalanching within one or more semiconductors. In some instances this release of leakage inductance energy may cause increased EMI/RFI and switch stresses. It is well known in the art to employ a “snubber” circuit of various arrangements (e.g., 214 and 216 ) to dissipate or recapture a part of this energy. The switch signal 110 is driven via an amplifier or gate driver or directly by a controller as described above in connection with FIG. 1A . The input voltage across terminals 218 and 220 may be positive or negative, although the circuit in FIG. 2A is operable for the potential at terminal 218 to be higher than the potential at terminal 220 . The output voltage across terminals 222 and 224 may be positive or negative. In the specific embodiment illustrated in FIG. 2A the potential at terminal 222 is higher than potential at terminal 224 . The relationship between potentials at terminals 218 , 220 , 222 , and 224 may be arbitrary in embodiments of the flyback circuits described herein, but the type of switch, orientation of transformer poles and rectifier, connectivity of capacitor 226 etc., must be consistent with that arrangement. For best efficiency, the turns ratio of transformer 206 may be tailored to the range of input vs. output voltages.

Embodiments of the present invention may confer the advantage of reduced stress on switch 202 and rectifying diodes as well as reduced EMI/RFI. This addition comprises a capacitor 226 used to transfer energy associated with a large rate of voltage change from the secondary to primary and vice-versa. In some embodiments, capacitor 226 is connected such that it couples the primary 204 and secondary 208 winding of transformer 206 . In some embodiments, capacitor 226 is in a circuit from transformer terminals having the same polarity. In some embodiments, the coupled primary terminal is on the switch side of the circuit. Capacitor 226 does not appear in conventional flyback converters and the use of other types of capacitor, e.g., a SEPIC power-transfer capacitor, is detrimental to the cost and operating envelope of an isolated flyback converter. Capacitor 226 may reduce stress, EMI/RFI, and shunting of a portion of otherwise lost power from the snubber circuit, during a relatively short span of the switching cycle associated with the release of leakage-inductance energy. For best electrical efficiency, it may be beneficial to limit this span to less than 20% and preferably less than 10% of the switch period. Furthermore, it may be beneficial to limit the average power transfer associated with this capacitor to less than 10% and in some embodiments, less than 5% of the power transfer of the converter. The use of a capacitor having an excessively large capacitance may result in reduced circuit efficiency. An excessively large capacitance moreover may increase the cost of this component and may not be economically justified compared to the benefit. In some embodiments of the present invention, the capacitance of capacitor 226 is in the pico-Farad (pF) range. In a particular embodiment, the capacitance is between 5 pF and 50 pF.

In some embodiments, capacitor 226 may be used in a flyback converter having a winding ratio from secondary to primary greater than 1 and preferably greater than 4. In some embodiments, the voltage rating of capacitor 226 is chosen to exceed or meet the expected peak voltages it experiences. In some embodiments, capacitor 226 is of ceramic or film composition. In other embodiments, capacitor 226 may feature one or more of low-cost, long life, stable capacitance, and low-loss at frequencies in the 100 kHz-100 MHz range and preferably in the range up to or beyond 1000 MHz.

The capacitor choice may be dictated by economy and intended use. In some embodiments, capacitor 226 has a ceramic C0G or NP0 or mica dielectric. In other embodiments, the capacitor dielectric may be of class-2 composition, e.g., X7R, Y5V, etc. Other embodiments may employ a “Gimmick” capacitor. A particular embodiment may employ the capacitance between planes in a printed circuit board. An advantage of this approach is that it requires no additional components and may exploit conductor planes and traces that would otherwise exist for current and heat-conduction considerations. The parallel plate size of such a capacitor for typical FR4 printed circuits is typically of the order of 500 mm.sup.2 or smaller, depending on the dielectric thickness. A disadvantage of this approach may be that it requires some control over the printed-circuit dielectric, which may increase cost. In some embodiments, voltage breakdown may apply a constraint on the minimum dielectric thickness.

FIG. 2B shows a schematic diagram of an isolated flyback power circuit 240 showing an embodiment of sensing signals that may be used in the operation of a switch controller. Element 242 is a current-sensing resistor, typically in the sub-Ohm range and in the sub-0.1 Ohm range in a particular embodiment. The current passing through resistor 242 produces a relatively low-level voltage signal 244 that can be used directly or amplified, filtered, modulated etc. to provide a suitable signal for a controller. Alternatively, a current measurement may use other techniques known in the art, including a hall-effect sensor, thermal sensor, measurement of core saturation, measurement of voltage drop across a non-ideal element such as a switch, inductor, transformer winding etc. Alternatively, the current may be inferred from a calculation. Elements 246 and 248 comprise a resistive voltage divider circuit that may comprise a part or entirety of circuit to sense input-voltage 250 for use in the operation of some embodiments of switching controllers according to the present invention. Elements 252 and 254 comprise a voltage divider that may similarly produce in part or whole an output voltage signal 256 for use in some embodiments of a controller that employ such information. Other embodiments may infer this information in other ways. Some embodiments may utilize a signal derived from a terminal 258 of a switch 260 in order to measure and infer the instantaneous or average operating state of the power circuitry. In some embodiments, filtering may be employed to prevent damage or excessive noise from affecting the controller operation or radiating EMI/RFI, since this node of the circuit may be subject to relatively high voltage, high-frequency spikes.

Switch Algorithm

Referring back to FIG. 2A , when switch 202 opens in the isolated flyback converter a substantial part of the energy stored in transformer 206 is applied to one or more secondary-side circuits. Typically, the energy flows through rectifier 210 as a current into a low-impedance, e.g., a capacitor 212 , which reduces output voltage swing. At some point in the discharge, the output voltage supported by the energy being released by transformer 206 drops below the output voltage of rectifier 210 and the rectifier becomes reverse biased. At this point, the residual energy in transformer 206 has no outlet and the voltage at the transformer terminals undergoes an under-damped oscillation, reflecting the oscillation of currents internal to transformer 206 . Via these oscillating currents, transformer 206 stores this residual energy, which can range up to several percent of the converted energy.

FIG. 3A shows an oscilloscope trace 300 of the voltage across the secondary winding 208 of transformer 206 having a 1:10 turns ratio from a single primary to a single secondary winding. FIG. 3B shows a simultaneous trace of the voltage across switch 202 (taken at position 258 illustrated in FIG. 2B ). The time period 302 and switch voltage 322 corresponds with the time that switch 202 is conducting and transformer 206 is storing energy magnetically. The period 304 and switch voltage 324 corresponds to the part of the switch cycle in which switch 202 is turned off (non-conducting) and stored energy is being transferred to the output side, which in this embodiment is a load at about 100 V. The time interval 306 and voltage waveform 326 is the remaining period that switch 202 is off during the switching cycle, herein called the “ring duration.” The voltage swings, e.g., 308 and 326 , reveal the oscillation caused by residual energy in transformer 206 . The interval 310 is the natural oscillation period of this energy, herein called the “ring period,” p.sub.ring. The brief period of voltage spiking 328 is caused by the discharge of energy stored in the leakage inductance of transformer 206 . In this embodiment, this energy is damped in part by resistors 214 and capacitor 216 and redistributed by capacitor 226 , which may provide for increased efficiency and lower EMI/RFI. The discontinuity in the voltage at location 330 may be associated with a loss of efficiency and less than optimal transfer of power to the output.

FIG. 3C shows an oscilloscope trace 340 of the switch voltage at a lower current setting. The ring duration 344 is longer than 306 and more oscillations from the residual energy are evident. The voltage discontinuity at the start 342 of the switching cycle is more pronounced than that at 330 . Embodiments of the present invention mitigate this discontinuity and set the ring duration to maximize efficiency.

Depending on the ring duration, i.e., the timing of the next switch cycle relative to the internal oscillation, this residual energy can be transferred back to the primary side, kept in transformer 206 , where damping and switch losses may convert it to heat, or transferred to the secondary side. The converter power efficiency is highest when the residual energy is transferred to the secondary. Embodiments of the present invention cost-effectively coordinate switch on-time and duration (alternatively, duty-cycle and frequency) parameters to maximize the transfer of residual energy to the secondary. This condition is a form of soft switching and has the additional advantages of reducing EMI/RFI and switch and rectifier stresses, among others.

Some conventional controllers employ a fixed switch period. FIG. 4 shows a plot 400 of converter efficiency at various switch periods vs. input current at constant input and output voltage. Efficiency peaks at various input currents e.g., 402 , 404 that depend on the switch frequency. The large indicated drop in efficiency at low current 406 is an artifact of non-ideal behavior of the programmable load used in to make these measurements. The present invention may vary the switch frequency to ensure operation at an efficiency peak over a wide range of input and output conditions.

FIG. 5 shows a plot 500 of the input current and converter efficiency at constant input and output Voltage and switch frequency (period) vs. switch duty cycle (width). Efficiency peaks 502 and troughs 504 correspond respectively to low-slope 506 and high-slope 508 regions of the current vs. switch width curve, consequently, some embodiments in accordance with the present invention employ at least an algorithm that adjusts the switch timing to operate in a region having a minimum dependence of current on switch width, a minimum finite-difference-based derivative of the current with width (e.g., min(ΔI.sub.in/Δw), min(ΔI.sub.out/Δw)), or a zero finite-difference based second derivative of the current with width (e.g., Δ.sup.2I.sub.in/Δw.sup.2=0, Δ.sup.2I.sub.out/Δw.sup.2=0). The low efficiency in region 510 is an artifact of a non-ideal programmable load. We observe regions of operation in which the current actually decreases with increasing switch width or duty cycle. In some embodiments, it may be important for a closed-loop controller to check for and adapt its control strategy for this regime.

Embodiment so the present invention relate to how many cycles of the internal ringing to allow during a switch cycle. Because of losses and non-idealities in components throughout the converter, the most efficient choice varies with the input and output voltage and current. Lower currents generally favor a greater number of rings, corresponding to a lower switching period. At a given output voltage, as input currents increase, the optimal ring duration drops in discrete intervals substantially corresponding to the ring period. FIG. 6 contains results taken from a comprehensive scan of discrete switch settings supported by hardware PWM, in accordance with an embodiment of the present invention. Plot 600 shows the peak recorded efficiencies and the corresponding switch period vs. input current at a fixed input and output voltage, but a variable switch width and period. The maximum switch period was limited arbitrarily in this scan to approx. 13.3 μs (75 kHz). The minimum switch period was limited to about 5 μs (200 kHz). As evidenced in the plot, truncation of the minimum switch period scan range may not have affected the results, since the minimum period that produced a peak efficiency result 602 was approximately 6.6 μs. Truncation of the maximum period affects the performance at low current 604 and high current 606 . Such truncation may be needed because of hardware limitations, ripple requirements, etc. Some preferred embodiments of such scans do not truncate the scan range. Some embodiments scan adaptively to provide coverage of regions of particular interest (e.g., peak efficiency) while avoiding excessive scan time on unfavorable states.

FIG. 7 shows a plot 700 of the calculated ring duration corresponding to the peak-efficiency states shown in FIG. 6 . The ring duration is calculated using a simple expression: t .sub.ring =p −( w+δw )[1+η.sup.1/2 ρV .sub.in/( V .sub.out +δV )],

where δw is a parameter that accounts for rise and fall times and other reasons that the effective switch width may differ from the width applied to a PWM circuit, η is measured converter efficiency, ρ is the secondary-to-primary windings ratio, and δV accounts for any forward voltage drop in an output rectifier (e.g., 210 ).

As evidenced by patterns in plot 600 above, peak operating conditions fall into substantially contiguous groups herein called “bands,” including 608 / 702 , 610 / 704 , 612 / 706 , 614 / 708 , 616 / 710 , 618 / 712 , 620 / 714 , and 622 / 716 . These bands respectively contain 7, 6, 5, 4, 3, 2, 1, and 0 complete ring periods. In scans in which the maximum period is not truncated as severely, we observe similar groupings having more than twelve complete ring periods at low currents. Because of measurement noise, PWM quantization, and physical phenomena within the converter, the minimum and maximum currents spanned by elements of the bands may overlap. In such cases, the efficiency differences between the bands may be negligible.

Above a threshold current (e.g., near 602 ), a controller according to the present invention may transition to a scheme in which the switching is synchronized such that the ring duration is a fraction of the ring period 716 and the period increases approximately linearly with input current. Above a higher threshold current (e.g., near 624 ), the converter may transition to switch timing having approximately the same slope and intercept in the period/input-current curve, but a discretely longer switch width, resulting in a shorter ring duration by a fraction of the ring period 718 . This mode may continue until a maximum period is reached, e.g., near 606 , defined by hardware limitations or ripple requirements, etc., or a maximum switch width is reached, e.g., defined by peak-current limitations, etc.

At higher load currents still, there may be a transition to an alternate operating mode, having an approximately zero or slightly negative ring period 720 , according to transformer charging and discharging times. The curves of most efficient switch period and width vs. input current in this regime 626 break dramatically from the near-linear, positive-slope ramps associated with the lower-current regimes, but are similarly amenable to simplification and incorporation into open and closed loop switch-control systems. Operation in this regime allows a substantial increase in transferred power for given hardware at the expense of some loss of efficiency 628 and greater stresses, particularly in the rectifier. Some preferred embodiments of the present invention constrain the operation to avoid this alternative mode. Some embodiments of the present invention avoid this alternative mode when it may cause damage to the unit, e.g., because of ambient temperature, input and output voltage and current, etc.

FIG. 8 contains a plot 800 that is similar to plot 600 described above, but showing an overlay of operation at different input and output voltages. These plots reveal similar features, such as discrete bands, e.g., 802 , but different band slopes and intercepts and different band termini (e.g., 804 ). From an analysis of data over a wide range of input and output conditions, it can be seen that the optimum transitions between bands are substantially dictated by an input current parameter” I*=I.sub.in/V.sub.out. At input-to-output voltage ratios near the winding ratio of the transformer, the slopes and intercepts of the bands are also substantially dictated by I*, that is, the bands in a plot like 800 with the current axis of each data set scaled by the inverse of the respective output Voltage lie substantially atop each other in clear and discrete groups. However, for ratios of input to output voltage that depart from the winding ratio significantly, the band slopes and intercepts vary in a manner that may resemble, but depart from a simple-theoretical analysis of switch solution loci having a prescribed number of ring periods (integral and fractional) in the ring duration. A part-empirical, part-theoretical approach to producing an effective model of this variation can be of use for control purposes. This approach revealed that, at a given voltage ratio, a common correction factor applied to the slopes of each band and another common correction factor applied to the intercepts of each band could reproduce experimental results with reasonable fidelity.

The description continues in the full USPTO document.