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Method for the fabrication of semiconductor integrated circuit device

US 2010/0227461 A1 · Assignee: RENESAS TECHNOLOGY CORP. · Inventors: Ochi; Hironori

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Listed from its USPTO record in Patent Yard's full-term archive. Its claims, description and drawings are in the USPTO PDF and on Google Patents, and the Claude kit works from them.

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Why it's free to use

  • Published September 9, 2010, and no patent has issued anywhere in its US family since.
  • Nothing has been filed in its family for more than seven years, so it is very unlikely to still be pending.
  • This status is inferred from USPTO records. Confirm it on Patent Center before relying on it.
FiledFebruary 27, 2010
PublishedSeptember 9, 2010
StatusAbandoned (inferred)
Application number12/714487
Classification (CPC)H10D30/0227 +2 more
Length35 pages

Timeline

Timeline From USPTO dates

Application filedFeb 27, 2010Application publishedSep 9, 2010

Sources & verification

Official USPTO records

Full published documentText and every drawing sheet as a PDF.USPTOFile historyStatus, office actions, notices, fee records and petitions.USPTO Patent CenterPatent Public Search recordSearchable full text and bibliographic data.USPTO

Cross-check elsewhere

Google PatentsFull text, worldwide family, citing patents and legal events.patents.google.comJustia PatentsFull text, claims and classification.patents.justia.comFreePatentsOnlineFull text and PDF.freepatentsonline.comEspacenetForeign family and legal status.European Patent Office

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