A high speed dram achitecture with uniform access latency

Abstract From the Canadian patent

A Dynamic Random Access Memory (DRAM) performs read write, and refresh operations. The DRAM includes a plurality of sub-arrays each having a plurality of memory cells each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device the column select device, and the read write, and refresh operations in response to a word line timing pulse. The read write, and refresh operation are performed in the same amount of time.