High speed zero dc power programmable logic device (pld) architecture
CA 2499277 A1 · Owner: Payne, James E. · Inventors: Kuo, Harry H.; Nguyen, Victor V.; Pathak, Saroj
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells (Fig.3). Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit (330-333) a settable , latch (320-323), a signal path means (360A 360B), and an output logic gate , (350). The signal-path means coupled to the cell unit the settable latch, and , the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block (402-408) for a modular low power consumption, high speed zero DC current, high noise , immunity programmable logic device (PLD) (700) which includes an array …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed August 6, 2003. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended August 6, 2023.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by August 6, 2025.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.