Direct memory swapping between nand flash and sram with error correction coding
CA 2476913 A1 · Owner: Higgins, Richard · Inventors: Higgins, Richard; Rodrigues, Brian; Wei, Jian
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g. an SRAM) operative to provide storage of data, a second storage unit (e.g. a NAND Flash) operative to provide (mass) storage of data an EMI unit implemented , within an ASIC and operative to provide control signals for the storage units and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC and each storage unit is operable , to store data from the other storage unit via the data bus when the other storage …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed February 21, 2003. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended February 21, 2023.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by February 21, 2025.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.