Method for generating design constraints for modulates in a hierarchical integrated circuit design system
CA 2450135 A1 · Owner: Riepe, Michael A. · Inventors: Burks, Timothy M.; Swanson, Robert M.; Riepe, Michael A.
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a timing budget by examining said estimated arrival times at said blocks pins.
Read the whole patent
Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed June 10, 2002. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended June 10, 2022.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by June 10, 2024.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.