Buffer circuit having reduced leakage current and method of reducing leakage current in a field programmable device

Abstract From the Canadian patent

A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters and ground or power. NMOS and PMOS transistors are added to selected buffers comprised of two inverters in series. The PMOS transistor (124) is connected between the first inverter (112,114) and power (Vdd) and the NMOS transistor (126) is connected between the second inverter (128) and ground. The added transistors are controlled by a memory cell (130) to be on when the buffer is being used and off when the buffer is unused. Alternatively no PMOS transistor is added , and an existing PMOS transistor of the first inverter is manufactured to sit in a …