Prioritized instruction scheduling for multi-streaming processors

Abstract From the Canadian patent

A multi-streaming processor (14) has multiple streams (4) for processing multiple threads (1-3), and an instruction scheduler (5) including a priority record of priority codes (7, 8) for one or more of the streams (4). The priority codes (7, 8) determine in some embodiments relative access to resources (10-13) as well as which stream (4) has access at any point in time. In other embodiments priorities are determined dynamically and altered on-thefly, which may be done by various criteria such as on-chip processing , statistics by executing one or more priority algorithms by input from off-, chip (9), according to stream loading or by combinations of these and other methods. In one …