A bus arrangement and associated method in a computer system

Abstract From the Canadian patent

A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter in a second or subsequent , clock cycle the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.