Distributed instruction completion logic

Abstract From the Canadian patent

Each execution unit within a superscalar processor has an associated completion table that, contains a copy of the status of all instructions dispatched but not completed. A central completion, table maintains the status of every dispatched instruction as reported by the dispatch unit and the, individual execution units. Execution units send finish signals to the completion table responsible, for retiring a particular type of instruction. The central completion table retires instructions that may, cause an interrupt and instructions whose results may target the same register. The execution units', associated completion tables retire the balance of the instructions and the execution …