Programmable input/output circuit for fpga for use in ttl, gtl, gtlp, lvpecl and lvds circuits
CA 2260504 C · Owner: Ghia, Atul V. · Inventors: Ghia, Atul V.; Menon, Suresh Manohar; Bobra, Yogendra Kumar
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A programmable input/output structure comprised of three input circuits and one output circuit coupled to the pin of an FPGA with the input circuits and output circuits being selectively enabled by programming bits so that input signals may be accepted from TTL GTL, GTLP, LVPECL or LVDS type external circuits. The programming bits can also selectively enable an output driver to simultaneously drive the same pin of the FPGA as an output with signals which are either TTL or GTL or GTLP compatible. Further the slew rate of the output driver is programmable between slow medium or fast.
Read the whole patent
Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed January 27, 1999 and granted August 19, 2003. A Canadian patent filed from October 1, 1989 lasts 20 years from filing, so its term ended January 27, 2019.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by January 27, 2021.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.