Method and system for simultaneous variable-width bus access in a multiprocessor system

Abstract From the Canadian patent

A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions each processor outputs, a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pending transactions at that processor, all pending transactions are performed in parallel on separate …