Computer memory controller

Abstract From the Canadian patent

A computer memory controller comprises a DRAM timing control section that provides, during memory back-up operation mode, self-refresh timing to DRAM array having self-refresh function. It also comprises a refresh/back-up control section that provides information as to memory back-up state to the DRAM timing control section. A DRAM identification mode register is provided. When DRAM array without self-refresh function is mounted, the state of the register changes. The state of the register is fed to the DRAM timing control section, thereby to provide timing according to the conventional CBR refresh method to the DRAM array.