Clock skew management method and apparatus

Abstract From the Canadian patent

A method of testing an integrated circuit having core logic with two or more clock domains and at least one signal path originating in one clock domain and terminating in an other clock domain, each signal path having a source control element in the one clock domain and an associated destination control element inthe other clock domain each the control element being a scannable memory element, the method comprising the steps of for each the control element shifting a test stimulus into all scannable elements in the core logic; placing an associated source control element in a hold mode for a predetermined number of clock cyclesprior to a capture operation so that the source control element …