Digital phase locked loop

Abstract From the Canadian patent

A digital phase locked loop is for recovering a stable clock signal from at least one input signal subject to fitter is disclosed. The loop comprises a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator and a, tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled …