Pll circuit and noise reduction means for pll circuit
CA 2192881 C · Owner: Ichihara, Masaki · Inventors: Ichihara, Masaki
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A phase-locked loop frequency synthesizer circuit having reduced phase noise comprises a voltage controlled oscillator for generating and outputting a signal of frequency corresponding to an input control voltage a frequency divider triggered by either of a rising edge or a falling edge of an output signal of the voltage controlled oscillator for dividing the output signal of the voltage controlled oscillator a flip-flop triggered by one of the rising edge and the falling edge of the output signal of the voltage controlled oscillator that is not used as a trigger of the frequency divider for taking and outputting the output signal of the frequency divider a reference clock generator for …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed December 13, 1996 and granted July 4, 2000. A Canadian patent filed from October 1, 1989 lasts 20 years from filing, so its term ended December 13, 2016.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by December 13, 2018.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.