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Canadian application, no grantCanada

Method for protecting netlists provided for simulation

CA 2130239 A1 · Owner: Little, Vernon Robert · Inventors: Smith, Graham Bennett; Huscroft, Charles Kevin; Little, Vernon Robert

CIPO record

Overview

Drawings and full text

Its claims, description and drawings are in the Canadian Patents Database.

Open the CIPO record

Abstract From the Canadian patent

A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.

Read the whole patent

Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.

Why it's free to use

  • Filed August 16, 1994. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended August 16, 2014.
  • A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by August 16, 2016.
  • We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
FiledAugust 16, 1994
GrantedNo grant recorded
Term endedAugust 16, 2014
Patent numberCA 2130239 A1
Classification (IPC)H03K19/00 +1 more

Timeline

Timeline From CIPO dates

1995199719992001200320052007200920112013Application filedAug 16, 1994Term endedAug 16, 2014

Sources & verification

Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.