Digital clock dejitter circuits for regenerating clock signals with minimal jitter

Abstract From the Canadian patent

A digital clock dejitter circuit includes a RAM (20) for receiving an incoming gapped signal (14a), a digital fractional RAM full-, ness gauge (30) for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator (40) for receiving a fast clock signal and the control indication and for providing, therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge (30) comprises write (54) and read (56) counters which track the movement of data into and out of the RAM, and a subtractor (58) for taking the difference of the counters …