Symmetrical multi-layer metal logic array with continuous substrate taps

Abstract From the Canadian patent

A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell (100) includes a four transistor arrangement in which a substrate tap (308) is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps (304 308, 314), outside of the transistors the power line connections can be routed in a simple and efficient manner. In addition the gate array architecture mirrors pairs of transistor columns (302, 306, 310, 312) for the sharing of substrate taps (308) between pairs of columns. This mirroring feature further reduces routing complexity.