Method and system for indexing the assignment of intermediate storage buffers in a superscalar processor system
CA 2112995 A1 · Owner: Kau, Chin-Cheng · Inventors: Kau, Chin-Cheng; Waldecker, Donald Emil; Ogden, Aubrey Deene
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A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers a plurality of, general purpose registers and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
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- Filed January 6, 1994. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended January 6, 2014.
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