Receiver having clock phase memory for receiving short preamble time slots

Abstract From the Canadian patent

A clock phase signal of each time slot of a TDM signal is stored into a corresponding memory location and a clock phase signal of a subsequent time slot is read from a memory location corresponding to the subsequent time slot for recovering clock pulses. A decoder is synchronized with the clock pulses for decoding an encoded digital signal of each time slot to produce a decoded signal. The error rate of the decoded signal of each time slot is decoded and compared with a prescribed value. When the detected error rate is determined to be higher than the prescribed value the write operation of the memory is disabled to prevent the clock phase signal stored in a memory location corresponding to …