Method and system for nonsequential instruction dispatch and execution in a superscalar processor system
CA 2107305 A1 · Owner: Kahle, James Allen · Inventors: Waldecker, Donald Emil; Kahle, James Allen
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction permitting the, …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed September 29, 1993. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended September 29, 2013.
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Timeline
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Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.