Method and system for single cycle dispatch of multiple instructions in a superscalar processor system

Abstract From the Canadian patent

A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit a particular one, of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction permitting the instruction to be dispatched within a single cycle by …