Apparatus for implementing interrupts in pipelined processors

Abstract From the Canadian patent

In a computing system of the type which executes instructions having the form A op B - B a floating point, register includes a plurality of addressable storage elements for storing operand data. A first address receiving circuit receives the B operand address from a first instruction and a, second address receiving circuit receives the A operand address from the first instruction. The A and B operand addresses are each used for addressing one of the plurality of floating point register storage elements. An instruction executing circuit performs a function designated by the first instruction on the operand data output from the floating point register and generates result data. The …