Phase adjustment method and apparatus for use in a clock recovery circuit

Abstract From the Canadian patent

The present disclosure includes a discussion of a method of phase adjustment for use in a clock recovery scheme. The phase adjustment circuit automatically holds the clock phase during periods of poor channel quality. The clock recovery scheme generates a sampling clock signal (139) which is synchronous with the received signal (131). Additionally the clock recovery, scheme generates at least two error signals (347 349, 351, 353) which indicate the quality of the received signal at different sampling phases. The smallest error signal is referred to as the minimum error value. Each error signal (347 349, 351, 353) is, compared to the minimum error value creating a corresponding normalized …