Time delay control for serial digital video interface audio receiver buffer

Abstract From the Canadian patent

An audio receiver FIFO memory buffer in the serial digital video interface allows improved timing synchronization between video and audio information. Furthermore, it eliminates unpleasant sound effects when multiple data samples are skipped or repeated in series. This FIFO receiver buffer receives data at an input write-data rate filling up the memory storage cells therein. An output read-data signal clocks the data out of the memory storage cells. The FIFO's fullness is monitored and maintained in response to, an external signal, to within a specified range delimited by an upper and a lower threshold. If the FIFO buffer fullness is below the range's lower threshold, then the FIFO's read …