Low power noise rejecting ttl to cmos input buffer

Abstract From the Canadian patent

A low power, noise rejecting TTL-to-CMOS input buffer, without the use of a current consuming voltage reference, has the, characteristic of recognizing a logic LOW as less than 0.8 volts and a logic HIGH as greater than 2.0 volts for DC TTL signals while drawing only leakage current from its Vcc power supply and simultaneously possesses the characteristic of rejecting high-amplitude Vin noise. For an input signal rapidly rising from zero to three volts, the buffer output switches at an input signal level of approximately 2.5 volts; and for the input signal rapidly falling from 3 to zero volts, the buffer output switches at an input signal level of approximately 1.4 volts.