Combined queue for invalidates and return data in multiprocessor system
CA 2045756 C · Owner: Digital Equipment Corporation · Inventors: Bouchard, Gregg; Chisvin, Lawrence
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed June 26, 1991 and granted August 20, 1996. A Canadian patent filed from October 1, 1989 lasts 20 years from filing, so its term ended June 26, 2011.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by June 26, 2013.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
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Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.