Burst address sequence generator
CA 2045224 A1 · Owner: Acer Incorporated · Inventors: Chan, Wan-Kan
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A kind of burst address sequence generator (10) is to generate 2n pulse trains (n is an integer greater than l) compatible with INTEL 80486 CPU including the, following: One n-bit binary up counter (11) whose input, terminal inputs a signal of one first pulse train address (ZERO#) for initializing and to begin counting and an increment signal (INC) used to trigger the input. The output terminal has n count signal C(0 ... n-1) to, couple to n corresponding XOR gates (12): one transparent latch (13), whose input terminal inputs n address bit A(m, ... m+n-1) signals (in other words 2n, pulse train burst cycles with size of each transmission data at 2m bytes; A0~A(M-1) as the continuous lowest …
Read the whole patent
Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Filed June 21, 1991. No grant is recorded for it in Canada; had it been granted, its 20-year term would have ended June 21, 2011.
- A certificate of supplementary protection adds at most two years for a drug, so even that would have ended by June 21, 2013.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.