Memory access control having commonly shared pipeline structure

Abstract From the Canadian patent

In a memory access controller, request data is received from a selected request source, specifying the mode of access to a main memory (30), and is supplied to a first pipeline (50) in which it is periodically shifted along its stages. A second pipeline (51) is connected to the output stage of the first pipeline if request data at that stage indicates partial-write mode. Store data is also received during full-write or partial-write mode and stored into a source data register (21) and a buffer (22). A first controller (10) receives request data from the input stage of the first pipeline (50) for accessing the memory in a read mode if it indicates read or partial-write mode or accessing it …