Electronic circuit for generating error detection codes for digital signals

Abstract From the Canadian patent

An electronic circuit, for generating error detection codes from digital signals organized into serial data blocks, in which the error code is derived from the coefficients of a remainder polynomial obtained from the division by a suitable divisor polynomial of a dividend polynomial whose coefficients are the bits of each serial block, is implemented by feedback through adders within shift register. A reset of the register necessary at the beginning of each serial data block and the loading of a first data bit of the block are both performed in a single clock interval, by using flip-flops to form the register which have alternative inputs one of which is used during reception of the first …