Avoiding latent errors in a logic network for majority select ion of binary signals

Abstract From the Canadian patent

A circuit and a method for avoiding latent errors in a logic network for majority selection of binary signals in a triplicated system. Errors which result from errors or faults in one of two or more parallel-connected transistors of one or more separate logic devices included in the logic network are avoided by repeatedly switching each of the separate logic devices in a manner such that transistors which were parallel-connected become series-connected and, vice versa. As a result, these devices will perform alternately logic operations which are the dual correspondence of one another, e.g. NAND- and NOR-operations with the aid of the same transistors in both instances. Thus, in practice, …