Apparatus and method for increased operand availability in a data processing unit with a store through cache memory unit strategy

Abstract From the Canadian patent

In a data processing system in which each of the data processing units is implemented using pipeline techniques and has a cache memory unit employing a store through strategy, the time required to prepare a write instruction operand address can be substantially shorter than the time required by the execution unit to prepare the associated write instruction operand. In order to utilize time difference, apparatus is included in the execution (E-)cache unit for storing the write instruction operand address during the preparation of the associated write instruction operand. After storing the write instruction operand address, a next address is entered in an input register of the E-cache unit. …