Data delay circuit and clock extraction circuit using the same

Abstract From the Canadian patent

A data delay circuit includes a first transistor, and a second transistor having a base an, emitter and a collector. Input data is applied to the bases of the first and second transistors. A constant-current source is coupled between the emitters of the first and second transistors and a negative power source. A capacitor is connected between the collector of the first transistor and the collector of the second transistor. The data delay circuit further includes a third transistor and a fourth transistor. The emitters of the third and fourth transistors ar connected to the collectors of the first and second transistors, respectively. The bases of the third and fourth transistors are …