Test chip for use in semiconductor fault analysis

Abstract From the Canadian patent

A semiconductor test chip for use in semiconductor fabrication fault analysis, comprises an n x m array of transmission gate cells arranged such that within a given row respective strips of conductive material of a first type form common source and drain electrodes for the transistors of the row, the sources and drains of each row being independent and within a column strips of conductive material of a second type form common gate electrodes such that each column of transistors can be turned on independently. An input circuit permits a predetermined bit pattern to be selectively applied to the inputs of the rows of transmission gate cells. A demultiplexer including output transmission gates …