Clock controlling unit capable of controlling supply of a clock signal in a computer system comprising arithmetic processors connected in series

Abstract From the Canadian patent

In a computer system comprising first through K-th arithmetic processors connected to a control section (18) in an ascending order, where K represents a positive integer which is not less than two a, memorizing unit (20) memorizes first and second information. A clock controlling unit (21) detects a fault signal produced by a k-th arithmetic processor where k represents one of 1 through K. When the memorizing unit memorizes the first information the, controlling unit controls a supplying unit (19) to put the k-th through the K-th arithmetic processors out of operation. When the memorizing unit memorizes the second information, the controlling unit controls the supplying unit to put the …