Cache unit capable of efficiently insuring cache coherence

Abstract From the Canadian patent

In a multiprocessor system including a plurality of cache units which are connected in common to a main storage (20) and to instruction processing units respectively, each cache unit (3n) comprises a flag circuit (5n) divided into a plurality of flag bit areas (FA-1 to FA-M) which correspond to block areas (BA-1 to BA-M) of a cache memory (4n). Each flag bit area memorizes a flag bit corresponding to a block memorized in the corresponding block area to indicate presence or absence of one of memory blocks in a common memory area of the main storage in correspondence to the memorized block. Supplied with a cache clear request (CRn) from an n-th one (1n) of the instruction processing units a, …