Single bus graphics data processing pipeline

Abstract From the Canadian patent

Stages of a graphics data processing pipeline are interconnected by a common bus far conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address …