Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system

Abstract From the Canadian patent

In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme rather than by, the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer 30 is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. A translation buffer fixup unit 52 is employed to update the translation buffer 30 with the most recently accessed physical memory locations. Therefore, subsequent …