Microinstruction addressing in high-speed cpu

Abstract From the Canadian patent

A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle before, a microinstruction could be decoded then the data on the, read bus, or data from the write bus is used and the, pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.