Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory

Abstract From the Canadian patent

In a multi-processing computer system including a plurality of central processing units (CPUs) and input/output (I/O) units, a system memory including a plurality of DRAM-based memory segments a system control, unit (SCU) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of system memory, and an interface for establishing communication between the SCU and the system memory and regulating the transfer of memory commands and associated data therebetween, the system memory is configured in the form of at least one independently accessible memory unit having a first dedicated data path for the transfer of read …