Write-read/write-pass memory subsystem cycle
CA 1323446 C · Owner: Gagliardo, Michael A. · Inventors: Tessari, James E.; Chinnaswamy, Kumar; Lynch, John J.
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU and a, second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted October 19, 1993. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended October 19, 2010.
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Timeline
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Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.