Active dynamic memory cell

Abstract From the Canadian patent

Abstract A dynamic memory cell comprises a storage transistor and an access transistor. The gate of the storage transistor is utilized as a storage capacitor electrode, and is connected to its source by a high resistance resistor. The drain of the storage transistor is connected to a source of electrical potential (e.g. Vcc). The access transistor connects the source of the storage transistor to a bit line. This arrangement multiplies the effective capacitance of tile gate storage capacitor reducing the area required and hence making the structure more compact than a typical inactive (one transistor) DRAM cell. In a preferred embodiment the, resistor is formed to overlie the storage …