Phase adjusting circuit

Abstract From the Canadian patent

A phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock, comprising a plurality of registers; inputting each bit of the data into a corresponding one of the plurality of registers in a predetermined cyclic order synchronized with a receiving clock which is extracted from the data, and outputting outputs of the registers in parallel. The outputs are each selected in a selector circuit under a control of the selector control signal in the same order as the above input into the registers. The selector control signal is generated by detecting a phase relationship between phases of the receiving clock and the system clock, and generating a …