Memory device and method implementing wordline redundancy without an access time penalty

Abstract From the Canadian patent

The invention provides a semiconductor memory device and method for implementing wordline redundancy with no access penalty in such a device. A redundant word decoder compares an incoming address signal with a list of defective addresses and, in response to the comparison, produces at least one comparison signal to control the propagation of a redundant driver signal along at least one redundant wordline. A main trigger receives the comparison signal and, in response thereto, triggers the firing of a main wordline driver to produce a main driver signal. The main wordline driver and the redundant word decoder are responsive to opposite states of the comparison signal such that, for a given …