Image processor with free flow pipeline bus

Abstract From the Canadian patent

A digital image processing system (10) has a pipeline bus (30) for transferring addresses and data in parallel among the components of the system which include an, image memory (16), an address generator (18) and an intensity processor (20). The pipeline bus (30) includes a pipeline address bus (34), a pipeline data bus (36) and a master, timing bus (38). Through the use of handshake signals the, pipeline bus (30) permits a free flow of pipelined data among the components at whatever rate is necessary to complete the particular processing task. Image data is transferred in the form of N x N pixel subimage blocks which can be addressed using a single address.