Microprocessor vectored interrupts

Abstract From the Canadian patent

A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.