Marching interconnecting lines in semiconductor integrated circuits
CA 1305255 C · Owner: Lynch, William Thomas · Inventors: Lynch, William Thomas; Lebowitz, Joseph
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Abstract, In order to reduce parasitic capacitive cross-coupling in an integrated circuit, metallization lines in an array--for example an array of word lines, of bit, lines, or of bus interconnects-are geometrically arranged in a systematically progressive marching sequence, whereby the identity of the lines located on either side of a given line keeps changing.
Read the whole patent
Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted July 14, 1992. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended July 14, 2009.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.